JP4021104B2 - バンプ電極を有する半導体装置 - Google Patents

バンプ電極を有する半導体装置 Download PDF

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Publication number
JP4021104B2
JP4021104B2 JP22284799A JP22284799A JP4021104B2 JP 4021104 B2 JP4021104 B2 JP 4021104B2 JP 22284799 A JP22284799 A JP 22284799A JP 22284799 A JP22284799 A JP 22284799A JP 4021104 B2 JP4021104 B2 JP 4021104B2
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Japan
Prior art keywords
semiconductor device
bump electrode
protective film
bump
film
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Expired - Fee Related
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JP22284799A
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Japanese (ja)
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JP2001053100A (ja
JP2001053100A5 (enExample
Inventor
紀幸 木村
聖明 門井
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Seiko Instruments Inc
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Seiko Instruments Inc
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Priority to JP22284799A priority Critical patent/JP4021104B2/ja
Priority to US09/632,324 priority patent/US6563216B1/en
Publication of JP2001053100A publication Critical patent/JP2001053100A/ja
Publication of JP2001053100A5 publication Critical patent/JP2001053100A5/ja
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Publication of JP4021104B2 publication Critical patent/JP4021104B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP22284799A 1999-08-05 1999-08-05 バンプ電極を有する半導体装置 Expired - Fee Related JP4021104B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP22284799A JP4021104B2 (ja) 1999-08-05 1999-08-05 バンプ電極を有する半導体装置
US09/632,324 US6563216B1 (en) 1999-08-05 2000-08-04 Semiconductor device having a bump electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22284799A JP4021104B2 (ja) 1999-08-05 1999-08-05 バンプ電極を有する半導体装置

Publications (3)

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JP2001053100A JP2001053100A (ja) 2001-02-23
JP2001053100A5 JP2001053100A5 (enExample) 2005-11-24
JP4021104B2 true JP4021104B2 (ja) 2007-12-12

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JP22284799A Expired - Fee Related JP4021104B2 (ja) 1999-08-05 1999-08-05 バンプ電極を有する半導体装置

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US (1) US6563216B1 (enExample)
JP (1) JP4021104B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008462B2 (en) 2015-09-18 2018-06-26 Samsung Electronics Co., Ltd. Semiconductor package

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
KR100448344B1 (ko) * 2002-10-22 2004-09-13 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 제조 방법
US6864578B2 (en) * 2003-04-03 2005-03-08 International Business Machines Corporation Internally reinforced bond pads
US7180195B2 (en) * 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing
JP4010311B2 (ja) * 2004-09-06 2007-11-21 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
JP4606145B2 (ja) * 2004-12-09 2011-01-05 セイコーエプソン株式会社 半導体装置及びその製造方法
DE102005009358B4 (de) * 2005-03-01 2021-02-04 Snaptrack, Inc. Lötfähiger Kontakt und ein Verfahren zur Herstellung
US20060211167A1 (en) * 2005-03-18 2006-09-21 International Business Machines Corporation Methods and systems for improving microelectronic i/o current capabilities
US8319343B2 (en) * 2005-09-21 2012-11-27 Agere Systems Llc Routing under bond pad for the replacement of an interconnect layer
US7952206B2 (en) * 2005-09-27 2011-05-31 Agere Systems Inc. Solder bump structure for flip chip semiconductor devices and method of manufacture therefore
JP4708148B2 (ja) * 2005-10-07 2011-06-22 ルネサスエレクトロニクス株式会社 半導体装置
JP4738971B2 (ja) * 2005-10-14 2011-08-03 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
US8552560B2 (en) * 2005-11-18 2013-10-08 Lsi Corporation Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing
US7888257B2 (en) * 2007-10-10 2011-02-15 Agere Systems Inc. Integrated circuit package including wire bonds
EP2195837A1 (en) * 2007-10-31 2010-06-16 Agere Systems Inc. Bond pad support structure for semiconductor device
JP2008047943A (ja) * 2007-11-01 2008-02-28 Renesas Technology Corp 半導体装置
JP4585564B2 (ja) * 2007-12-13 2010-11-24 ルネサスエレクトロニクス株式会社 半導体装置
JP2008160168A (ja) * 2008-03-26 2008-07-10 Seiko Epson Corp 半導体装置及びその製造方法
JP2010267641A (ja) * 2009-05-12 2010-11-25 Panasonic Corp 半導体装置
JP5259674B2 (ja) * 2010-10-18 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置
KR102658923B1 (ko) 2016-09-12 2024-04-18 삼성전자주식회사 반도체 장치 및 반도체 패키지

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US5220199A (en) * 1988-09-13 1993-06-15 Hitachi, Ltd. Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
JPH04212426A (ja) * 1990-06-21 1992-08-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3238011B2 (ja) * 1994-07-27 2001-12-10 株式会社東芝 半導体装置
US5686762A (en) * 1995-12-21 1997-11-11 Micron Technology, Inc. Semiconductor device with improved bond pads
US6022792A (en) * 1996-03-13 2000-02-08 Seiko Instruments, Inc. Semiconductor dicing and assembling method
KR100307385B1 (ko) * 1997-03-05 2001-12-15 구본준, 론 위라하디락사 액정표시장치의구조및그제조방법
KR100255591B1 (ko) * 1997-03-06 2000-05-01 구본준 박막 트랜지스터 어레이의 배선 연결 구조 및 그 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008462B2 (en) 2015-09-18 2018-06-26 Samsung Electronics Co., Ltd. Semiconductor package

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JP2001053100A (ja) 2001-02-23
US6563216B1 (en) 2003-05-13

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