JP3866111B2 - 半導体集積回路及びバーンイン方法 - Google Patents

半導体集積回路及びバーンイン方法 Download PDF

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Publication number
JP3866111B2
JP3866111B2 JP2002009500A JP2002009500A JP3866111B2 JP 3866111 B2 JP3866111 B2 JP 3866111B2 JP 2002009500 A JP2002009500 A JP 2002009500A JP 2002009500 A JP2002009500 A JP 2002009500A JP 3866111 B2 JP3866111 B2 JP 3866111B2
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Japan
Prior art keywords
circuit
output
voltage
level conversion
external
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Japanese (ja)
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JP2003218687A5 (enExample
JP2003218687A (ja
Inventor
繁充 田原
大介 片桐
健 嶋貫
雅史 大柴
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Renesas Technology Corp
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Renesas Technology Corp
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Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2002009500A priority Critical patent/JP3866111B2/ja
Priority to US10/309,183 priority patent/US6777997B2/en
Priority to US10/352,238 priority patent/US20030137337A1/en
Publication of JP2003218687A publication Critical patent/JP2003218687A/ja
Priority to US10/865,890 priority patent/US20040222837A1/en
Priority to US11/153,355 priority patent/US7109779B2/en
Publication of JP2003218687A5 publication Critical patent/JP2003218687A5/ja
Application granted granted Critical
Publication of JP3866111B2 publication Critical patent/JP3866111B2/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
JP2002009500A 2002-01-18 2002-01-18 半導体集積回路及びバーンイン方法 Expired - Fee Related JP3866111B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2002009500A JP3866111B2 (ja) 2002-01-18 2002-01-18 半導体集積回路及びバーンイン方法
US10/309,183 US6777997B2 (en) 2002-01-18 2002-12-04 Semiconductor integrated circuit and a burn-in method thereof
US10/352,238 US20030137337A1 (en) 2002-01-18 2003-01-28 Semiconductor integrated circuit and a burn-in method thereof
US10/865,890 US20040222837A1 (en) 2002-01-18 2004-06-14 Semiconductor integrated circuit and a burn-in method thereof
US11/153,355 US7109779B2 (en) 2002-01-18 2005-06-16 Semiconductor integrated circuit and a burn-in method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002009500A JP3866111B2 (ja) 2002-01-18 2002-01-18 半導体集積回路及びバーンイン方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2006237667A Division JP2007049719A (ja) 2006-09-01 2006-09-01 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2003218687A JP2003218687A (ja) 2003-07-31
JP2003218687A5 JP2003218687A5 (enExample) 2005-07-21
JP3866111B2 true JP3866111B2 (ja) 2007-01-10

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Family Applications (1)

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JP2002009500A Expired - Fee Related JP3866111B2 (ja) 2002-01-18 2002-01-18 半導体集積回路及びバーンイン方法

Country Status (2)

Country Link
US (4) US6777997B2 (enExample)
JP (1) JP3866111B2 (enExample)

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* Cited by examiner, † Cited by third party
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JP2003347926A (ja) * 2002-05-30 2003-12-05 Sony Corp レベルシフト回路、表示装置および携帯端末
US7282981B2 (en) * 2002-11-06 2007-10-16 Nec Corporation Level conversion circuit with improved margin of level shift operation and level shifting delays
TWI229499B (en) * 2003-10-01 2005-03-11 Toppoly Optoelectronics Corp Voltage level shifting circuit
JP4489403B2 (ja) * 2003-10-10 2010-06-23 株式会社ルネサステクノロジ 半導体集積回路装置
GB2421105B (en) * 2003-10-10 2006-08-09 Advanced Risc Mach Ltd Level shifting in a data processing apparatus
US20050268124A1 (en) * 2004-05-25 2005-12-01 Hewlett-Packard Development Company, L.P. Apparatus and method for voltage switching
US20050270065A1 (en) * 2004-06-03 2005-12-08 Dipankar Bhattacharya Coms buffer having higher and lower voltage operation
JP2006303753A (ja) * 2005-04-19 2006-11-02 Renesas Technology Corp 半導体集積回路装置
JP4750599B2 (ja) * 2006-03-29 2011-08-17 シチズンホールディングス株式会社 電子回路
KR101205323B1 (ko) * 2006-09-28 2012-11-27 삼성전자주식회사 리텐션 입/출력 장치를 이용하여 슬립모드를 구현하는시스템 온 칩
JP4823024B2 (ja) * 2006-11-09 2011-11-24 株式会社東芝 レベル変換回路
JP5412992B2 (ja) * 2009-06-26 2014-02-12 富士通セミコンダクター株式会社 集積回路装置及びデータ伝送システム
JP5589853B2 (ja) * 2011-01-05 2014-09-17 富士通セミコンダクター株式会社 レベル変換回路及び半導体装置
US8705282B2 (en) * 2011-11-01 2014-04-22 Silicon Storage Technology, Inc. Mixed voltage non-volatile memory integrated circuit with power saving
US8723584B2 (en) * 2012-05-03 2014-05-13 Conexant Systems, Inc. Low power dual voltage mode receiver
CN103513176B (zh) * 2012-06-21 2016-06-01 和硕联合科技股份有限公司 测试主板的屏蔽电路及其屏蔽方法
CN105207658B (zh) * 2014-06-11 2018-03-27 华邦电子股份有限公司 输出缓冲器
KR102387233B1 (ko) * 2015-10-20 2022-04-19 에스케이하이닉스 주식회사 버퍼 회로
US11223359B2 (en) 2016-03-31 2022-01-11 Qualcomm Incorporated Power efficient voltage level translator circuit
CN106788386B (zh) * 2016-11-30 2021-08-06 上海华力微电子有限公司 一种降低热载流子劣化的电平转换电路
JP6873876B2 (ja) * 2017-09-21 2021-05-19 株式会社東芝 駆動回路

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Publication number Priority date Publication date Assignee Title
US3816765A (en) * 1972-06-27 1974-06-11 Rca Corp Digital interface circuit for a random noise generator
US4739193A (en) * 1986-10-30 1988-04-19 Rca Corporation Drive circuit with limited signal transition rate for RFI reduction
JPH07105160B2 (ja) * 1989-05-20 1995-11-13 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
US5216298A (en) * 1989-12-14 1993-06-01 Mitsubishi Denki Kabushiki Kaisha ECL input buffer for BiCMOS
US5315167A (en) * 1992-04-09 1994-05-24 International Business Machines Corporation Voltage burn-in scheme for BICMOS circuits
KR970008141B1 (ko) * 1994-11-15 1997-05-21 엘지반도체 주식회사 반도체장치의 번인회로
JPH098632A (ja) 1995-06-23 1997-01-10 Nec Corp 半導体集積回路
DE69618123T2 (de) * 1995-09-21 2002-06-13 Matsushita Electric Industrial Co., Ltd. Ausgangsschaltung
JP4074697B2 (ja) * 1997-11-28 2008-04-09 株式会社ルネサステクノロジ 半導体装置
JP3796034B2 (ja) * 1997-12-26 2006-07-12 株式会社ルネサステクノロジ レベル変換回路および半導体集積回路装置
JP2000353947A (ja) 1999-06-10 2000-12-19 Matsushita Electric Ind Co Ltd レベル変換装置
US6353345B1 (en) * 2000-04-04 2002-03-05 Philips Electronics North America Corporation Low cost half bridge driver integrated circuit with capability of using high threshold voltage DMOS
JP3502330B2 (ja) * 2000-05-18 2004-03-02 Ｎｅｃマイクロシステム株式会社 出力回路
JP2002107418A (ja) * 2000-09-28 2002-04-10 Hitachi Ltd 半導体装置の製造方法
JP3532181B2 (ja) * 2001-11-21 2004-05-31 沖電気工業株式会社 電圧トランスレータ
TWI271035B (en) * 2002-01-11 2007-01-11 Samsung Electronics Co Ltd Receiver circuit of semiconductor integrated circuit
JP3935925B2 (ja) * 2002-03-04 2007-06-27 富士通株式会社 出力バッファ回路
US6586974B1 (en) * 2002-05-08 2003-07-01 Agilent Technologies, Inc. Method for reducing short circuit current during power up and power down for high voltage pad drivers with analog slew rate control

Also Published As

Publication number Publication date
US20030137340A1 (en) 2003-07-24
US6777997B2 (en) 2004-08-17
US20040222837A1 (en) 2004-11-11
US7109779B2 (en) 2006-09-19
US20050231262A1 (en) 2005-10-20
JP2003218687A (ja) 2003-07-31
US20030137337A1 (en) 2003-07-24

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