JP3715637B2 - めっき方法 - Google Patents
めっき方法 Download PDFInfo
- Publication number
- JP3715637B2 JP3715637B2 JP2004069421A JP2004069421A JP3715637B2 JP 3715637 B2 JP3715637 B2 JP 3715637B2 JP 2004069421 A JP2004069421 A JP 2004069421A JP 2004069421 A JP2004069421 A JP 2004069421A JP 3715637 B2 JP3715637 B2 JP 3715637B2
- Authority
- JP
- Japan
- Prior art keywords
- plating
- resist layer
- semiconductor wafer
- negative resist
- exposure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000007747 plating Methods 0.000 title claims description 155
- 238000000034 method Methods 0.000 title claims description 65
- 239000004065 semiconductor Substances 0.000 claims description 62
- 229920002120 photoresistant polymer Polymers 0.000 claims description 51
- 239000004020 conductor Substances 0.000 claims description 10
- 235000012431 wafers Nutrition 0.000 description 64
- 230000002093 peripheral effect Effects 0.000 description 31
- 239000002184 metal Substances 0.000 description 20
- 229910052751 metal Inorganic materials 0.000 description 20
- 230000001681 protective effect Effects 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
- G03F7/203—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electroplating Methods And Accessories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
半導体ウェハの上面に導体層を形成する導体層形成工程と、
前記導体層の上面にネガ型レジスト層を形成するレジスト層形成工程と、
ステップ式投影露光装置により、前記ネガ型レジスト層を所定領域毎に露光する第1の露光工程と、
前記第1の露光工程の実施後に、前記ネガ型レジスト層の外周部を露光する第2の露光工程と、
露光された前記ネガ型レジスト層に対し現像処理を行ない所定のめっきパターンを形成する現像工程と、
前記めっきパターンにめっきを行なうめっき工程とを備えることを特徴とするものである。
請求項1記載のめっき方法において、
前記ネガ型レジスト層として、10μm以上の厚さを有するものを用いたことを特徴とするものである。
請求項2記載のめっき方法において、
前記ネガ型レジスト層として、ドライフィルムレジストを用いたことを特徴とするものである。
請求項1乃至3の何れか1項に記載のめっき方法において、
前記めっき工程で実施されるめっき処理時に、シールめっき治具を用いることを特徴とするものである。
110 導通メタル層
120 ネガ型レジスト層
140 外周露光領域
150 めっきパターン
160 めっき治具
161 マスク治具
162 裏蓋治具
180 めっき装置
182 めっき液
184 カソード電極
185 アノード電極
200 単位露光領域
Claims (4)
- 半導体ウェハの上面に導体層を形成する導体層形成工程と、
前記導体層の上面にネガ型レジスト層を形成するレジスト層形成工程と、
ステップ式投影露光装置により、前記ネガ型レジスト層を所定領域毎に露光する第1の露光工程と、
前記第1の露光工程の実施後に、前記ネガ型レジスト層の外周部を露光する第2の露光工程と、
露光された前記ネガ型レジスト層に対し現像処理を行ない所定のめっきパターンを形成する現像工程と、
前記めっきパターンにめっきを行なうめっき工程と、
を備えることを特徴とするめっき方法。 - 請求項1記載のめっき方法において、
前記ネガ型レジスト層として、10μm以上の厚さを有するものを用いたことを特徴とするめっき方法。 - 請求項2記載のめっき方法において、
前記ネガ型レジスト層として、ドライフィルムレジストを用いたことを特徴とするめっき方法。 - 請求項1乃至3の何れか1項に記載のめっき方法において、
前記めっき工程で実施されるめっき処理時に、シールめっき治具を用いることを特徴とするめっき方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004069421A JP3715637B2 (ja) | 2004-03-11 | 2004-03-11 | めっき方法 |
US11/072,724 US7790359B2 (en) | 2004-03-11 | 2005-03-04 | Plating method |
TW094106931A TW200536063A (en) | 2004-03-11 | 2005-03-08 | Plating method |
KR1020050019919A KR20060043811A (ko) | 2004-03-11 | 2005-03-10 | 도금 방법 |
CNB200510054563XA CN100533686C (zh) | 2004-03-11 | 2005-03-11 | 电镀方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004069421A JP3715637B2 (ja) | 2004-03-11 | 2004-03-11 | めっき方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2005256090A JP2005256090A (ja) | 2005-09-22 |
JP2005256090A5 JP2005256090A5 (ja) | 2005-11-04 |
JP3715637B2 true JP3715637B2 (ja) | 2005-11-09 |
Family
ID=34918491
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004069421A Expired - Fee Related JP3715637B2 (ja) | 2004-03-11 | 2004-03-11 | めっき方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7790359B2 (ja) |
JP (1) | JP3715637B2 (ja) |
KR (1) | KR20060043811A (ja) |
CN (1) | CN100533686C (ja) |
TW (1) | TW200536063A (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007299960A (ja) * | 2006-04-28 | 2007-11-15 | Toshiba Corp | 半導体装置及びその製造方法 |
JP5247998B2 (ja) * | 2006-08-11 | 2013-07-24 | 株式会社テラミクロス | 半導体装置の製造方法 |
JP2009266995A (ja) * | 2008-04-24 | 2009-11-12 | Casio Comput Co Ltd | 半導体装置の製造方法 |
US20120261254A1 (en) * | 2011-04-15 | 2012-10-18 | Reid Jonathan D | Method and apparatus for filling interconnect structures |
JP5782398B2 (ja) | 2012-03-27 | 2015-09-24 | 株式会社荏原製作所 | めっき方法及びめっき装置 |
CN102707566A (zh) * | 2012-05-22 | 2012-10-03 | 上海宏力半导体制造有限公司 | 光刻方法 |
JP6328582B2 (ja) * | 2014-03-31 | 2018-05-23 | 株式会社荏原製作所 | めっき装置、および基板ホルダの電気接点の電気抵抗を決定する方法 |
CN105575880B (zh) * | 2014-10-09 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制作方法 |
CN104538287B (zh) * | 2014-11-24 | 2017-08-11 | 通富微电子股份有限公司 | 半导体制造电镀治具密封接触光阻区域形成方法 |
US10014170B2 (en) | 2015-05-14 | 2018-07-03 | Lam Research Corporation | Apparatus and method for electrodeposition of metals with the use of an ionically resistive ionically permeable element having spatially tailored resistivity |
CN106773537B (zh) * | 2016-11-21 | 2018-06-26 | 中国电子科技集团公司第十一研究所 | 一种基片的表面光刻和湿法刻蚀方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3391125B2 (ja) | 1994-12-15 | 2003-03-31 | 株式会社デンソー | 半導体ウエハ用メッキ治具 |
JP4037504B2 (ja) | 1998-01-09 | 2008-01-23 | 株式会社荏原製作所 | 半導体ウエハのメッキ治具 |
JP3415089B2 (ja) * | 1999-03-01 | 2003-06-09 | 住友金属鉱山株式会社 | プリント配線板の製造方法 |
JP3430290B2 (ja) * | 1999-11-26 | 2003-07-28 | カシオ計算機株式会社 | 半導体装置の製造方法 |
JP4649792B2 (ja) | 2001-07-19 | 2011-03-16 | 日本電気株式会社 | 半導体装置 |
JP2003151875A (ja) * | 2001-11-09 | 2003-05-23 | Mitsubishi Electric Corp | パターンの形成方法および装置の製造方法 |
-
2004
- 2004-03-11 JP JP2004069421A patent/JP3715637B2/ja not_active Expired - Fee Related
-
2005
- 2005-03-04 US US11/072,724 patent/US7790359B2/en active Active
- 2005-03-08 TW TW094106931A patent/TW200536063A/zh unknown
- 2005-03-10 KR KR1020050019919A patent/KR20060043811A/ko not_active Application Discontinuation
- 2005-03-11 CN CNB200510054563XA patent/CN100533686C/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN1667802A (zh) | 2005-09-14 |
US20050202346A1 (en) | 2005-09-15 |
US7790359B2 (en) | 2010-09-07 |
TW200536063A (en) | 2005-11-01 |
JP2005256090A (ja) | 2005-09-22 |
CN100533686C (zh) | 2009-08-26 |
KR20060043811A (ko) | 2006-05-15 |
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