TW201737363A - 半導體封裝件之製造方法及半導體封裝件 - Google Patents

半導體封裝件之製造方法及半導體封裝件 Download PDF

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Publication number
TW201737363A
TW201737363A TW106100195A TW106100195A TW201737363A TW 201737363 A TW201737363 A TW 201737363A TW 106100195 A TW106100195 A TW 106100195A TW 106100195 A TW106100195 A TW 106100195A TW 201737363 A TW201737363 A TW 201737363A
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Taiwan
Prior art keywords
material layer
layer
insulating material
hole
semiconductor element
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TW106100195A
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English (en)
Inventor
Kiyoaki Hashimoto
Yuko Yamamoto
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J-Devices Corp
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Publication of TW201737363A publication Critical patent/TW201737363A/zh

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Abstract

在此提供一種半導體封裝件之製造方法,其能夠比以往更為減少用以形成通孔之元件,進而形成通孔。所提供之半導體封裝件之製造方法包含以下步驟。於支撐板上形成絕緣材料層。於前述絕緣材料層形成通孔。於前述絕緣材料層上配置半導體元件,且前述半導體元件之電極位於前述通孔之上。去除前述支撐板。於前述絕緣材料層之相反於前述半導體元件之表面、前述通孔及前述半導體元件之前述電極之表面形成晶種層。於前述通孔形成金屬層。

Description

半導體封裝件之製造方法及半導體封裝件
本發明為關於一種於半導體元件鍍設配線之半導體封裝件之製造方法及半導體封裝件。
於內藏有如IC或LSI之主動元件(active device)之基板之製造流程中,一般藉由雷射加工而進行通孔之形成。此場合中,為了防止對於裝置之傷害,會於裝置上之鋁墊上形成底阻障金屬(Under Barrier Metal,UBM)(例如為銅製),且於形成於其上之絕緣材料層進行通孔加工。記載於做為文獻之日本專利公開案第2013-30593號公報(美國專利申請公開案第2013/0026650號說明書)之發明揭示關於如此通孔之形成。
日本專利公開案第2013-30593號公報(美國專利申請公開案第2013/0026650號說明書)(例如參照圖7A及圖7B)中,揭示具備半導體元件、電極墊(相當於前述之底阻障金屬)及有機基板(相當於前述之絕緣材料層)之結構,其中電極墊鄰接於半導體元件下方,有機基板鄰接於電極墊下方且形成有通孔。
於如此之結構中,藉由雷射而於有機基板形成通孔之場合中,有自有機基板之下方朝向半導體元件照射雷射之必要,但半導體元件應無法接受雷射之照射,故有預先於半導體元件之下之位置配置底阻障金屬(日本專利公開案第2013-30593號公報(美國專利申請公開案第2013/0026650號說明書)中為銅電極墊)之必要。
然而,前述記載於日本專利公開案第2013-30593號公報(美國專利申請公開案第2013/0026650號說明書)之發明中,具有所謂耗費材料成本之問題。
本發明有鑑於上述現實狀況,而具有一目的為提供一種半導體封裝件之製造方法,其能夠比以往更為減少用以形成通孔之元件,進而形成通孔。
關於本發明之一實施型態之半導體封裝件之製造方法包含以下步驟。於支撐板上形成絕緣材料層。於前述絕緣材料層形成通孔。於前述絕緣材料層上配置半導體元件,且前述半導體元件之電極位於前述通孔之上。去除前述支撐板。於前述絕緣材料層之相反於前述半導體元件之表面、前述通孔及前述半導體元件之前述電極之表面形成晶種層。於前述通孔形成金屬層。
關於本發明之其他實施型態之半導體封裝件包含半導體元件、接合材料層、絕緣材料層、晶種層、金屬層及焊料球。半導體元件於一表面露出電極。接合材料層配置於前述半導體元件之一表面。絕緣材料層配置於前述接合材料層之上,通孔貫通前述接合材料層及前述絕緣材料層以露出前述電極。晶種層自前述絕緣材料層之表面沿前述通孔之內壁面設置且接觸於前述電極。金屬層接觸於前述晶種層且埋入前述通孔。焊料球接觸於前述金屬層。
以下,將參照圖式說明本發明之實施型態。然而,本發明能夠以多種相異態樣實施,而並非解釋成限定於以下所例示之實施型態之記載內容。此外,為了更明確地說明,相較於實際的態樣,圖式中針對各個部分之幅寬、厚度、形狀等雖有以模式之方式表達之情形,但僅為一範例,而並非用以限定本發明之解釋。而且,於本說明書及各個圖式中,關於已出現之圖而已於先前描述之元件,與其相同的元件將標記相同符號,且將適當省略詳細的說明。
於本說明書中,某些元件或區域為其他元件或區域之「上(或下)」之場合中,除非另有特別限制,否則不僅含有此些元件位於其他元件或區域之「正上方(或正下方)」之場合,亦可含有位於其他元件或區域之上方(或下方)之場合。換言之,亦可含有於其他元件或區域之上方(或下方)之間含有其他構成元件之場合。
關於本實施型態之半導體封裝件10之製造方法,將使用圖1A至圖4B進行說明。圖1A為支撐板11及第一接合材料層12之剖面圖。如圖1A所示,於支撐板11之上形成第一接合材料層12。
第一接合材料層12為能夠接合支撐板11及絕緣材料層13(將於後述)之層體,且為能夠熱剝離或藉由UV光剝離之層體。第一接合材料層12之材質可例如使用能夠熱剝離之發泡黏著材料。舉例而言,由玻璃形成支撐板11之場合中,UV(紫外線)可通過支撐板11而照射至第一接合材料12,進而使支撐板11能夠藉由UV而剝離。
圖1B為支撐板11、第一接合材料層12、絕緣材料層13及第二接合材料層14之剖面圖。更如圖1B所示,於第一接合材料層12之上更形成絕緣材料層13,於絕緣材料層13之上更形成第二接合材料層14。藉此,亦可於支撐板11之上形成絕緣材料層13。舉例而言,絕緣材料層13可使用含有填充物之樹脂,亦可使用含有如此填充物之聚醯亞胺(polyimide)樹脂或環氧(epoxy)樹脂(但亦可不限定為此些材料)。
第二接合材料層14為一種層體,其能夠接合形成有後述之孔13a(參照圖1C)之絕緣材料層13及半導體元件16(參照圖2A),於加熱硬化前之B階狀態(反應之中間階段,雖藉由加熱而軟化材料並使材料膨脹,且與某種液體接觸時,為完全溶解或不溶解階段之狀態)具有可密合於由矽或矽化物構成之半導體元件16之密合性,且於加熱硬化工程中能夠保持通孔15之形狀。
第二接合材料層14之材質例如可使用聚醯亞胺之接合材料。如前所述之絕緣材料層13含有填充物之場合中,為了緩和硬力,且為了抑制填充物所發出之α射線而造成位元錯誤(bit error)的發生,有必要將第二接合材料層14之材料替換成聚醯亞胺等之晶圓塗覆材料。第二接合材料層14於B階狀態升溫時可能會流進通孔15之內部。為了抑制此情形,有必為到達某個溫度時可保持通孔15形狀之材質。
圖1C為於圖1B之結構形成通孔15之剖面圖。如圖1C所示,於絕緣材料層13及第二接合材料層14形成通孔15。通孔15(貫通孔、開口部)具有形成於絕緣材料層13之孔13a及形成於第二接合材料層14之孔14a。其中,通孔15中雖亦於第一接合材料層12形成有孔12a,但因之後會隨著支撐板11共同去除,而不必出現於半導體封裝件10之製品。
通孔15可藉由雷射加工(藉由雷射R進行加工)或鑽頭加工、壓模切割等之機械加工之至少一者而形成。其中,雷射R可例如使用熱加工雷射、二氧化碳雷射或UV-YAG雷射(固態雷射之UV類型)。此外,於形成通孔15時,亦有對支撐板11形成通孔之可能性,但因之後會去除支撐板11而亦可形成有通孔15。
另外,絕緣材料層13亦可使用感光性樹脂,而可藉由曝光顯影之方式形成通孔15。亦可使用遮罩(mask)進行電漿灰化(plasma ashing),亦可為形成銅之阻劑(resist),裝設遮罩,且僅對被加工部位進行電漿加工之方法。
圖2A為對於圖1C之結構自上方配置半導體元件16且形成樹脂密封材料層17之剖面圖。其中,絕緣材料層13接近第一接合材料層12之表面為第一面13X,絕緣材料層13接近第二接合材料層14之表面為第二面13Y。如圖2A所示,於成為圖1C之狀態後,以半導體元件16之電極16k位於通孔15之上之方式,將半導體元件16配置於絕緣材料層13之第二面13Y之上之第二接合材料14之上。如此一來,將半導體元件16直接對準並搭載且接合於具有通孔15之絕緣材料層13之後,藉由樹脂密封材料層17進行密封。
如此一來,藉由樹脂密封材料層17進行密封,而可更加提升通孔15與電極16k之間之位置精確度。另外,電極16k例如可使用由鋁所形成之鋁墊。
圖2B為自圖2A之結構去除支撐板11及第一接合材料層12之剖面圖。於成為圖2A之狀態之後,去除支撐板11。舉例而言,支撐板11由玻璃形成,令UV光朝向支撐板11而進行照射時,支撐板11可於第一接合材料層12之位置進行剝離。
如此一來,由於用以形成通孔15而接受雷射照射的是半導體封裝件10之結構中所不需要之支撐板11,故不需要以往用以形成通孔而接受雷射照射之底阻障金屬。
圖3A為上下顛倒配置圖2B之結構之剖面圖。圖3A之狀態中,第二接合材料層14及絕緣材料層13之總和厚度可例如形成為15 μm之程度。
圖3B為對於圖3A之結構形成晶種層18之剖面圖。如圖3B所示,從開放通孔15之位置,於絕緣材料層13之第一面13X(絕緣材料層13中與半導體元件16相反之表面)、通孔15及半導體元件16之電極16k形成晶種層(seed layer)18。
圖4A為於圖3B之結構形成金屬層21之剖面圖。如圖4A所示,於通孔15形成金屬層21。
本實施例中,晶種層18可藉由濺射Ti及Cu而形成。而且,可例如藉由電鍍而形成金屬層21。此場合中,不需要對於半導體元件16之電極16k進行特別的表面處理(以往則需要形成底阻障金屬(UBM)等元件),便可形成金屬層21。此外,於晶種層18之形成中,能夠取代Ti而使用Ta,或者能夠使用TiW、TiN等之阻障金屬,亦能夠適當變更材質。
再者,於前述之先前技術中,於形成底阻障金屬時,會例如於半導體元件16之上塗覆聚醯亞胺,且於電極16k之部位形成開口。而且,會於其上形成Ti/Cu晶種層,於鍍銅後蝕刻晶種以完成底阻障金屬。如此形成底阻障金屬層耗費工時。若根據本實施例之製法,則可降低其工時。
另外,亦可取代電鍍,而對於半導體元件16所具有之電極16k進行著鋅(zincate)處理之後,可藉由非電鍍方式形成晶種層18。於此場合中,能夠藉由更為廉價之非電解方式而形成晶種層18。
如前所述,此晶種層18可藉由濺射或非電鍍方式形成,雖於之後藉由電鍍或非電鍍形成金屬層21時會使用此晶種層18,但不使用於配線之部分亦可於之後藉由蝕刻而去除。
圖4B為形成有焊料阻劑層且設置有焊料球22之半導體封裝件10之剖面圖。如圖4B所示,自金屬層21之上施加焊料阻劑而形成焊料阻劑層。而且,以接觸於金屬層21之方式搭載焊料球22。藉此完成半導體封裝件10。
因此,所完成半導體封裝件10自半導體元件16之順序包含半導體元件16、第二接合材料層14、絕緣材料層13、晶種層18、金屬層21及焊料球22。第二接合材料層14形成於半導體元件16上。絕緣材料層13形成於第二接合材料層14之上,所形成之通孔15自半導體元件16之電極16k之上端之位置直接貫通第二接合材料層14及絕緣材料層13至絕緣材料層13之上端之位置。晶種層18形成於通孔15之內部。金屬層21形成於晶種層18之內部。焊料球22以接觸於金屬層21之方式配置。而且,前述之金屬層21雖舉鍍設形成為例,但亦可藉由鍍設以外之方法形成金屬層21。
換言之,所完成半導體封裝件10自半導體元件16之順序包含半導體元件16、第二接合材料層14、絕緣材料層13、晶種層18、金屬層21及焊料球22。半導體元件16於一表面露出電極16k。第二接合材料層14(接合材料層)配置於半導體元件16之一表面。絕緣材料層13配置於第二接合材料層114之上,通孔15貫通第二接合材料層14及絕緣材料層13以露出電極16k。晶種層18自絕緣材料層13之表面沿通孔15之內壁面設置且接觸於電極16k。金屬層21接觸於晶種層18且埋入通孔15。焊料球22接觸於金屬層21。其中,亦可將前述之晶種層18及接觸於晶種層18之金屬層21合稱為埋入電極。
如前所述,所形成之通孔15為沿半導體元件16之膜厚方向自半導體元件16之電極16k之上端之位置直接貫通第二接合材料層14及絕緣材料層13,而貫通至絕緣材料層13之上端之位置。其中,半導體元件16之電極16k接觸於晶種層18。而且,於本實施型態之方法中,因不需要底阻障金屬,故能夠建構成通孔15比電極16k更寬之結構。
相對於此,以往之結構中,因於半導體元件16之上形成有底阻障金屬,而可說有自底阻障金屬之上端直接貫通至絕緣材料層13之上端之可能性。而且,於底阻障金屬之上端至下方之位置,必須要確保底阻障金屬之幅寬為大於通孔之幅寬而與通孔之幅寬相異之尺寸幅寬。因此,無法自半導體元件16之電極16k之上端之位置直接貫通至絕緣材料層13之上端之位置。而且,半導體元件之電極與晶種層之間因配置有底阻障金屬,而無法成為半導體元件之電極接觸於晶種層之結構。此外,前述之直接(straight)除了如圖4B所示為沿半導體元件16之膜厚方向之場合以外,亦可含有如圖5B所示之自半導體元件16之膜厚方向傾斜之場合。
而且,以往必須確保對準裕度(alignment margin),此對準裕度要考量到半導體元件16之配置與尺寸之變異、於半導體元件16之上形成底阻障金屬時之底阻障金屬之配置與尺寸之變異以及配置於底阻障金屬之上且形成於絕緣材料層之通孔之配置與尺寸之變異。相對於此,根據前述之半導體封裝件10之製造方法,因不需要考量底阻障金屬之配置與尺寸之變異,故能夠擴大形成通孔,進而提升設計之自由度。
而且,以往之結構中,必須以半導體元件之電極之尺寸大於通孔之尺寸之方式利用雷射形成通孔。相對於此,根據前述之半導體封裝件10之製造方法,因雷射R不會照射半導體元件16之樹脂之部分(電極16k之周圍),故亦能夠以半導體元件16之電極16k之尺寸小於通孔15之尺寸之方式形成通孔15。如此之結果,能夠不必考量通孔15之尺寸而選擇小尺寸電極16k,故可實現電極16k之間距窄化。
更甚者,以往於通孔加工時,雷射R超出底阻障金屬之場合中會有破壞半導體元件16之風險,但根據本實施型態則不會有此風險。
而且根據此結構,半導體封裝件10中半導體元件16以上之結構高度(總和晶種層18與金屬層21之高度),以往雖為80 μm,但於半導體封裝件10之中則可減少至50 μm,原理上更可能考量到40 μm。
圖5A為圖4A之立體圖。如圖5A所示,於被絕緣材料層13之第一面13X之表面圍繞之區域內形成金屬層21。於此金屬層21之內側,通孔15受到遮蓋。
圖5B為照射雷射而於絕緣材料層13形成通孔15之通孔焊墊(via land)連接之結構之剖面圖。藉由雷射形成通孔15之場合中,通孔15之形狀為於絕緣材料層13中沿著自接近半導體元件16之第二面13Y朝向相反於半導體元件16之第一面13X之方向(自接近半導體元件16之位置朝向接近絕緣材料層13之位置之方向)(朝向遠離半導體元件16之方向)變窄之錐狀。換言之,絕緣材料層13及第二接合材料14中,愈接近雷射照射之位置,其孔截面積可愈大。雷射照射之位置相當於用以配置前述半導體元件16之位置。如圖5B所示,絕緣材料層13及第二接合材料層14中,通孔15之接近半導體元件16之位置之一倍幅寬,可形成為大於通孔15之遠離半導體元件16之位置之二倍幅寬。
圖6A繪示用於引線(lead)連接且藉由照射雷射而於絕緣材料層13形成通孔15之結構之剖面圖。圖6B為圖6A之立體圖。引線連接之場合中,其結構可為擴大形成於絕緣材料層13之通孔15,且金屬層21並非鍍設於通孔15內部之全部。換言之,金屬層21並非充滿於通孔15之內部,金屬層21可沿著通孔15之形狀以指定厚度形成。即使為如此之結構,亦能夠得到與前述圖1A~圖5B所說明之內容同樣的效果。
由於能夠以半導體元件16之電極16k尺寸小於通孔15之尺寸之方式形成通孔15,故能夠形成如圖6B所示之囊括開口(長孔)之通孔15,而可不為形成於內部之晶種層分別覆蓋電極16k且一部分電極16k受到遮蓋之小開口。
圖7A繪示半導體封裝件10之第一變形例之剖面圖。其中,半導體封裝件10可為與圖4B之範例實質上相同之結構,而相當於上下顛倒圖4B結構之結構。樹脂密封材料層17配置成覆蓋半導體元件16。而且,於半導體元件16之下方經由圖未繪示之第二接合材料14而配置有絕緣材料層13,且於此絕緣材料層13之下方配置焊料阻劑層23。於半導體元件16之電極16k之下方,通孔15形成於絕緣材料層13。於此通孔15之中及於絕緣材料層13之下形成金屬層21。再者,形成焊料阻劑層23,且於金屬層21之下搭載焊料球22。
此外,於此藉由雷射形成通孔15之場合中,通孔15之形狀亦可為沿著自接近半導體元件16之位置至接近絕緣材料層13之位置之方向變窄之錐狀。
圖8繪示半導體封裝件10之第二變形例之剖面圖。於此範例中,可上下並排半導體元件16。於各個半導體元件16之下可經由圖未繪示之第二接合材料14而形成有絕緣材料層13。再者,對於上下之各個絕緣材料層13形成通孔15,且於此通孔15之中及絕緣材料層13之下形成金屬層21。於下側之金屬層21之下形成焊料阻劑層23,且搭載多個焊料球22。而且,於下側之絕緣材料層13與焊料阻劑層23之間亦可配置絕緣材料層50。
而且,於此之樹脂密封材料層17亦可形成有通孔15,此通孔15之形狀亦可為沿著自接近下側絕緣材料層13之位置至接近下側半導體元件16之位置之方向(朝向上方之方向)變窄之結構,此結構之要點與圖7A之結構相異。
圖9繪示半導體封裝件10之第三變形例之剖面圖。此範例為用以於半導體封裝件10之上裝載半導體封裝件10之所謂的封裝件上封裝(package on package)之結構中之下段取向之構造。如圖9所示,於半導體封裝件10之上部位置,於半導體元件16之上配置用以能夠搭載其他半導體封裝件之連接用端子部21Z1。
而且,於此範例中,亦可於半導體元件16之下形成絕緣材料層13。於絕緣材料層13形成多個通孔15,於此些通孔15之中及絕緣材料層13之下形成金屬層21。於此,金屬層21具有分支,且於金屬層21之分支之間形成有絕緣材料層50。於金屬層21之下形成焊料阻劑層23,且搭載多個焊料球22。
其中,於此之樹脂密封材料層17亦形成有通孔15之要點雖與圖8之結構相同,但此通孔15之形狀為沿著自接近半導體元件16之位置至接近絕緣材料層13之位置之方向(朝向下方之方向)變窄之結構之要點,與圖8之結構相異。此外,焊料阻劑層23不僅形成於半導體元件16之下方而亦可形成於半導體元件16之上方之要點,與圖8之結構相異。另外,焊料阻劑層23亦可填充於樹脂密封材料層17之通孔15內。此結構之場合中,於此半導體元件16之上且配置有通孔15之區域以外之部分配置連接用端子部21Z1,且能夠於連接用端子部21Z1之上配置用以搭載於此半導體元件16上之另外封裝之半導體元件之端子。
圖10繪示半導體封裝件10之第四變形例之剖面圖。於此範例中,於半導體元件16上配置連接用端子部21Z1(配線層),且於更上方配置連接用端子部21Z2。因此,含有形成於樹脂密封材料層17之通孔15之正上方之上表面,亦能夠配置連接用端子。
於此範例中,亦可於半導體元件16之下形成絕緣材料層13。於絕緣材料層13形成多個通孔15。於此些通孔15之中及絕緣材料層13之下形成金屬層21。而且,於此之金屬層21具有分支,且於金屬層21之分支之間形成有絕緣材料層50。於金屬層21之下形成焊料阻劑層23,且搭載多個焊料球22。
其中,於此之樹脂密封材料層17亦形成有通孔15之要點雖與圖8之結構相同,但此通孔15之形狀為沿著自接近半導體元件16之位置至接近絕緣材料層13之位置之方向(朝向下方之方向)變窄之結構之要點,與圖8之結構相異。而且,絕緣材料層50不僅形成於半導體元件16之下方而亦可形成於半導體元件16之上方之要點,與圖9之結構相異。
圖7B繪示半導體封裝件10之第五變形例之剖面圖。如圖7B所示,於半導體元件16之橫向方向之端部側未配置電極16k之位置亦可配置有被動元件。此被動元件可例如使用電容器、電感器、電阻器等元件。
根據以上所說明之實施例及第一變形例至第五變形例之任一結構,於半導體元件16形成絕緣材料層13之工程中,不必以於半導體元件16附近(相鄰於電極16k)配置底阻障金屬之狀態照射雷射,便能夠於絕緣材料層13形成通孔15。如此之結果,不需要用於形成通孔15之底阻障金屬,而可實現半導體封裝件10之製造成本之降低。故在此能夠提供半導體封裝件之製造方法,其能夠比以往更為減少用以形成通孔之元件,進而形成通孔。
而且,所對應之結構能夠解除通孔15加工時破壞半導體元件16之風險,能夠提升設計自由度,且能夠藉由組合引線連接之結構而窄化連接墊間距。舉例而言,以往之方法於晶圓級封裝中,有使用感光性絕緣材料且藉由光微影而形成通孔之場合。此藉由光微影形成通孔之方法中,除了耗費材料成本以外,還殘有因絕緣材料之厚度限制而造成設計限制等問題。舉例而言,由於顯影工程中之解析度或因殘留應力而發生翹曲,故具有厚度限制。根據本實施型態之方法,而具有降低如此設計限制之優點。
從電性特性之觀點看來,除了能夠形成指定厚度之絕緣層以外,還能夠於關注翹曲時亦自由地選擇材料。如此之結果,為了能夠降低層間之電容,能夠增厚至相對於假定之15 μm更厚之程度。
此外,因能夠減少構成半導體封裝件10之材料種類,而能夠抑制半導體封裝件10之翹曲。更甚者,因於通孔15加工且晶粒附著(die attach)半導體元件16之後再以樹脂密封,故可緩和通孔15與半導體元件16間之偏移。
再者,以往使用底阻障金屬之場合中,由於通孔15形成為有底孔之形狀,故於雷射照射後難以去除殘留於通孔底部之樹脂。若去除如此殘留於通孔底部之所謂的去污工程進行不完全,金屬層21之接合面會夾有異物,而難以確保其可靠度。相對於此,根據實施例及第一至第五變形例之任一結構,照射雷射後去除通孔15底部之支撐板11及第一接合材料層12時,樹脂難以殘留。如此之結果,可易於確保半導體封裝件之可靠度。
10‧‧‧半導體封裝件
11‧‧‧支撐板
12‧‧‧第一接合材料層
12a‧‧‧孔
13‧‧‧絕緣材料層
13a‧‧‧孔
13X‧‧‧第一面
13Y‧‧‧第二面
14‧‧‧第二接合材料層
14a‧‧‧孔
15‧‧‧通孔
16‧‧‧半導體元件
16k‧‧‧電極
17‧‧‧樹脂密封層
18‧‧‧晶種層
21‧‧‧金屬層
22‧‧‧焊料球
23‧‧‧焊料阻劑層
30‧‧‧被動元件
50‧‧‧絕緣材料層
21Z1、21Z2‧‧‧連接用端子部
R‧‧‧雷射
X1、X2‧‧‧幅寬
圖1A為支撐板及第一接合材料層之剖面圖。 圖1B為支撐板、第一接合材料層、絕緣材料層及第二接合材料層之剖面圖。 圖1C為於圖1B之結構形成通孔之剖面圖。 圖2A為對於圖1C之結構自上方配置半導體元件且形成樹脂密封材料層之剖面圖。 圖2B為自圖2A之結構去除支撐板及第一接合材料層之剖面圖。 圖3A為上下顛倒配置圖2B之結構之剖面圖。 圖3B為對於圖3A之結構形成晶種層之剖面圖。 圖4A為於圖3B之結構形成金屬層之剖面圖。 圖4B為形成焊料阻劑且搭載焊料球之半導體封裝件之剖面圖。 圖5A為圖4A之立體圖。 圖5B為照射雷射而於絕緣材料層形成通孔之通孔焊墊連接之結構之剖面圖。 圖6A繪示用於引線連接且藉由照射雷射而於絕緣材料層形成通孔之結構之剖面圖。 圖6B為圖6A之立體圖。 圖7A繪示半導體封裝件之第一變形例之剖面圖。 圖7B繪示半導體封裝件之第五變形例之剖面圖。 圖8繪示半導體封裝件之第二變形例之剖面圖。 圖9繪示半導體封裝件之第三變形例之剖面圖。 圖10繪示半導體封裝件之第四變形例之剖面圖。
13‧‧‧絕緣材料層
13X‧‧‧第一面
13Y‧‧‧第二面
14‧‧‧第二接合材料層
15‧‧‧通孔
16‧‧‧半導體元件
16k‧‧‧電極
17‧‧‧樹脂密封層
18‧‧‧晶種層
21‧‧‧金屬層

Claims (10)

  1. 一種半導體封裝件之製造方法,包括:於一支撐板上形成一絕緣材料層;於該絕緣材料層形成一通孔;於該絕緣材料層上配置一半導體元件,該半導體元件之一電極位於該通孔之上;去除該支撐板;於該絕緣材料層之相反於該半導體元件之表面、該通孔及該半導體元件之該電極之表面形成一晶種層;以及於該通孔形成一金屬層。
  2. 如請求項1所述之半導體封裝件之製造方法,其中以一第一接合材料層黏著該支撐板及該絕緣材料層,該第一接合材料層能夠熱剝離或能夠藉由UV光剝離該支撐板及該絕緣材料層。
  3. 如請求項1所述之半導體封裝件之製造方法,其中以一接合材料層黏著該絕緣材料層及該半導體元件,該接合材料層於加熱硬化前之B階狀態具有密合於該半導體元件之密合性,且於加熱硬化工程中能夠保持該通孔之形狀。
  4. 如請求項2所述之半導體封裝件之製造方法,其中以一第二接合材料層黏著該絕緣材料層及該半導體元件,該第二接合材料層於加熱硬化前之B階狀態具有密合於該半導體元件之密合性,且於加熱硬化工程中能夠保持該通孔之形狀。
  5. 如請求項1至4之任一項所述之半導體封裝件之製造方法,其中藉由雷射加工、鑽頭加工及壓模切割之至少任一者形成該通孔。
  6. 如請求項1至4之任一項所述之半導體封裝件之製造方法,其中該絕緣材料層使用感光性樹脂,且該通孔為藉由曝光顯影而形成之孔。
  7. 如請求項1所述之半導體封裝件之製造方法,其中藉由濺射而形成該晶種層,且藉由電鍍而形成該金屬層。
  8. 如請求項1所述之半導體封裝件之製造方法,其中於該半導體元件所具有之該電極進行著鋅處理(zincate)之後,藉由非電鍍而形成該晶種層,且藉由電鍍而形成該金屬層。
  9. 一種半導體封裝件,包括:一半導體元件,於一表面露出一電極;一接合材料層,配置於該半導體元件之該表面;一絕緣材料層,配置於該接合材料層之上,一通孔貫通該接合材料層及該絕緣材料層以露出該電極;一晶種層,自該絕緣材料層之表面沿該通孔之內壁面設置且接觸於該電極;一金屬層,接觸於該晶種層且埋入該通孔;以及一焊料球,接觸於該金屬層。
  10. 如請求項9所述之半導體封裝件,其中該通孔之形狀為於該絕緣材料層中沿著自接近該半導體元件之表面朝向相反於該半導體元件之表面之方向變窄之錐狀。
TW106100195A 2016-01-15 2017-01-04 半導體封裝件之製造方法及半導體封裝件 TW201737363A (zh)

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EP2750490B1 (en) * 2011-08-23 2016-11-16 Fujikura Ltd. Component-mounting printed circuit board and manufacturing method for same
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