JP3660821B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP3660821B2
JP3660821B2 JP01101899A JP1101899A JP3660821B2 JP 3660821 B2 JP3660821 B2 JP 3660821B2 JP 01101899 A JP01101899 A JP 01101899A JP 1101899 A JP1101899 A JP 1101899A JP 3660821 B2 JP3660821 B2 JP 3660821B2
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JP
Japan
Prior art keywords
film
insulating film
forming
region
groove
Prior art date
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Expired - Fee Related
Application number
JP01101899A
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English (en)
Japanese (ja)
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JP2000208729A5 (enExample
JP2000208729A (ja
Inventor
勇 浅野
修 土屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP01101899A priority Critical patent/JP3660821B2/ja
Priority to TW088121013A priority patent/TW436958B/zh
Priority to US09/487,599 priority patent/US6238961B1/en
Priority to KR1020000002334A priority patent/KR20000057770A/ko
Publication of JP2000208729A publication Critical patent/JP2000208729A/ja
Publication of JP2000208729A5 publication Critical patent/JP2000208729A5/ja
Application granted granted Critical
Publication of JP3660821B2 publication Critical patent/JP3660821B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
JP01101899A 1999-01-19 1999-01-19 半導体装置およびその製造方法 Expired - Fee Related JP3660821B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP01101899A JP3660821B2 (ja) 1999-01-19 1999-01-19 半導体装置およびその製造方法
TW088121013A TW436958B (en) 1999-01-19 1999-12-01 Semiconductor integrated circuit device and process for manufacturing the same
US09/487,599 US6238961B1 (en) 1999-01-19 2000-01-19 Semiconductor integrated circuit device and process for manufacturing the same
KR1020000002334A KR20000057770A (ko) 1999-01-19 2000-01-19 반도체 집적 회로 장치 및 그 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01101899A JP3660821B2 (ja) 1999-01-19 1999-01-19 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2000208729A JP2000208729A (ja) 2000-07-28
JP2000208729A5 JP2000208729A5 (enExample) 2004-08-19
JP3660821B2 true JP3660821B2 (ja) 2005-06-15

Family

ID=11766385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01101899A Expired - Fee Related JP3660821B2 (ja) 1999-01-19 1999-01-19 半導体装置およびその製造方法

Country Status (4)

Country Link
US (1) US6238961B1 (enExample)
JP (1) JP3660821B2 (enExample)
KR (1) KR20000057770A (enExample)
TW (1) TW436958B (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10015278B4 (de) * 2000-03-28 2004-09-23 Infineon Technologies Ag Halbleiterspeicher mit einem Speicherzellenfeld
JP2002026008A (ja) * 2000-07-11 2002-01-25 Nec Corp 多層配線構造の形成方法及び多層配線構造が形成されたウエハ
US6573148B1 (en) * 2000-07-12 2003-06-03 Koninklljke Philips Electronics N.V. Methods for making semiconductor inductor
KR100709453B1 (ko) * 2001-06-27 2007-04-18 주식회사 하이닉스반도체 반도체소자의 비트라인 형성방법
US6620676B2 (en) * 2001-06-29 2003-09-16 International Business Machines Corporation Structure and methods for process integration in vertical DRAM cell fabrication
JP2004152878A (ja) * 2002-10-29 2004-05-27 Toshiba Corp 半導体記憶装置及びその製造方法
KR100560803B1 (ko) * 2004-02-04 2006-03-13 삼성전자주식회사 캐패시터를 갖는 반도체 소자 및 그 제조방법
US7485910B2 (en) * 2005-04-08 2009-02-03 International Business Machines Corporation Simplified vertical array device DRAM/eDRAM integration: method and structure
US20090159947A1 (en) * 2007-12-19 2009-06-25 International Business Machines Corporation SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION
KR101432619B1 (ko) * 2008-07-07 2014-08-21 삼성전자주식회사 반도체 장치 및 그 제조 방법
JP2016066775A (ja) 2014-09-18 2016-04-28 マイクロン テクノロジー， インク． 半導体装置及びその製造方法
US9704871B2 (en) * 2014-09-18 2017-07-11 Micron Technology, Inc. Semiconductor device having a memory cell and method of forming the same
US9698213B1 (en) * 2016-09-28 2017-07-04 International Business Machines Corporation Vertical MIM capacitor

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5219793A (en) * 1991-06-03 1993-06-15 Motorola Inc. Method for forming pitch independent contacts and a semiconductor device having the same
JP2765478B2 (ja) * 1994-03-30 1998-06-18 日本電気株式会社 半導体装置およびその製造方法
JP2806795B2 (ja) 1994-05-20 1998-09-30 日本電気株式会社 半導体集積回路の配線構造の製造方法
JPH0955440A (ja) * 1995-08-17 1997-02-25 Sony Corp 半導体装置及び半導体装置の製造方法
KR0168355B1 (ko) * 1995-11-02 1999-02-01 김광호 반도체장치의 배선 형성방법
JP3402022B2 (ja) * 1995-11-07 2003-04-28 三菱電機株式会社 半導体装置の製造方法
US5688713A (en) * 1996-08-26 1997-11-18 Vanguard International Semiconductor Corporation Method of manufacturing a DRAM cell having a double-crown capacitor using polysilicon and nitride spacers
JPH10163316A (ja) 1996-12-04 1998-06-19 Sony Corp 半導体装置における埋め込み配線の形成方法
JPH10178160A (ja) * 1996-12-17 1998-06-30 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP3614267B2 (ja) * 1997-02-05 2005-01-26 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
TW320765B (en) * 1997-02-22 1997-11-21 United Microelectronics Corp Manufacturing method of self-aligned contact of dynamic random access memory
US6008085A (en) * 1998-04-01 1999-12-28 Vanguard International Semiconductor Corporation Design and a novel process for formation of DRAM bit line and capacitor node contacts
US6054394A (en) * 1998-11-25 2000-04-25 United Microelectronics Corp. Method of fabricating a dynamic random access memory capacitor

Also Published As

Publication number Publication date
KR20000057770A (ko) 2000-09-25
US6238961B1 (en) 2001-05-29
JP2000208729A (ja) 2000-07-28
TW436958B (en) 2001-05-28

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