JP3655175B2 - 半導体記憶装置の製造方法 - Google Patents

半導体記憶装置の製造方法 Download PDF

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Publication number
JP3655175B2
JP3655175B2 JP2000199935A JP2000199935A JP3655175B2 JP 3655175 B2 JP3655175 B2 JP 3655175B2 JP 2000199935 A JP2000199935 A JP 2000199935A JP 2000199935 A JP2000199935 A JP 2000199935A JP 3655175 B2 JP3655175 B2 JP 3655175B2
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Japan
Prior art keywords
capacitor
single crystal
layer
field effect
vertical field
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Expired - Fee Related
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JP2000199935A
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English (en)
Japanese (ja)
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JP2002026279A (ja
JP2002026279A5 (enExample
Inventor
隆 川久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000199935A priority Critical patent/JP3655175B2/ja
Priority to US09/893,664 priority patent/US6544833B2/en
Publication of JP2002026279A publication Critical patent/JP2002026279A/ja
Publication of JP2002026279A5 publication Critical patent/JP2002026279A5/ja
Application granted granted Critical
Publication of JP3655175B2 publication Critical patent/JP3655175B2/ja
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Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
JP2000199935A 2000-06-30 2000-06-30 半導体記憶装置の製造方法 Expired - Fee Related JP3655175B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000199935A JP3655175B2 (ja) 2000-06-30 2000-06-30 半導体記憶装置の製造方法
US09/893,664 US6544833B2 (en) 2000-06-30 2001-06-29 Semiconductor memory device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000199935A JP3655175B2 (ja) 2000-06-30 2000-06-30 半導体記憶装置の製造方法

Publications (3)

Publication Number Publication Date
JP2002026279A JP2002026279A (ja) 2002-01-25
JP2002026279A5 JP2002026279A5 (enExample) 2004-10-28
JP3655175B2 true JP3655175B2 (ja) 2005-06-02

Family

ID=18697879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000199935A Expired - Fee Related JP3655175B2 (ja) 2000-06-30 2000-06-30 半導体記憶装置の製造方法

Country Status (2)

Country Link
US (1) US6544833B2 (enExample)
JP (1) JP3655175B2 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7205604B2 (en) * 2001-03-13 2007-04-17 International Business Machines Corporation Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof
JP2004214544A (ja) * 2003-01-08 2004-07-29 Fujitsu Ltd 半導体装置の製造方法
US6943407B2 (en) * 2003-06-17 2005-09-13 International Business Machines Corporation Low leakage heterojunction vertical transistors and high performance devices thereof
TWI294670B (en) 2003-06-17 2008-03-11 Ibm Ultra scalable high speed heterojunction vertical n-channel misfets and methods thereof
JP2005108876A (ja) * 2003-09-26 2005-04-21 Toshiba Corp 半導体装置及びその製造方法
US20050070043A1 (en) * 2003-09-30 2005-03-31 Koji Yamakawa Semiconductor device and method for manufacturing the same
KR100560803B1 (ko) * 2004-02-04 2006-03-13 삼성전자주식회사 캐패시터를 갖는 반도체 소자 및 그 제조방법
CN100539041C (zh) * 2004-10-22 2009-09-09 富士通微电子株式会社 半导体器件及其制造方法
JP4795677B2 (ja) * 2004-12-02 2011-10-19 ルネサスエレクトロニクス株式会社 半導体装置およびそれを用いた半導体モジュール、ならびに半導体装置の製造方法
US7326611B2 (en) * 2005-02-03 2008-02-05 Micron Technology, Inc. DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays
JP2006278674A (ja) 2005-03-29 2006-10-12 Nec Electronics Corp 電界効果トランジスタとその製造方法、及び半導体装置
JP2007305747A (ja) * 2006-05-10 2007-11-22 Nec Electronics Corp 半導体装置、及びコンデンサマイクロフォン
KR100971411B1 (ko) * 2008-05-21 2010-07-21 주식회사 하이닉스반도체 반도체 장치의 수직 채널 트랜지스터 형성 방법
JP2010129972A (ja) 2008-12-01 2010-06-10 Elpida Memory Inc 半導体装置およびその製造方法
TWI455291B (zh) * 2009-10-30 2014-10-01 Inotera Memories Inc 垂直式電晶體及其製造方法
JP5421317B2 (ja) * 2011-03-24 2014-02-19 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US9478736B2 (en) * 2013-03-15 2016-10-25 International Business Machines Corporation Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns
DE102015206175A1 (de) * 2015-04-07 2016-10-13 Globalfoundries Inc. Halbleiterbauelement mit Dünnschicht-Widerstand
KR102783332B1 (ko) * 2019-12-24 2025-03-20 삼성전자주식회사 반도체 소자 및 그의 제조 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691219A (en) 1994-09-17 1997-11-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor memory device
US5739563A (en) 1995-03-15 1998-04-14 Kabushiki Kaisha Toshiba Ferroelectric type semiconductor device having a barium titanate type dielectric film and method for manufacturing the same
DE19637389C1 (de) * 1996-09-13 1997-10-16 Siemens Ag Verfahren zur Herstellung einer DRAM-Zellenanordnung
US5990509A (en) * 1997-01-22 1999-11-23 International Business Machines Corporation 2F-square memory cell for gigabit memory applications
EP0899790A3 (de) * 1997-08-27 2006-02-08 Infineon Technologies AG DRAM-Zellanordnung und Verfahren zu deren Herstellung
JP3311276B2 (ja) 1997-08-29 2002-08-05 株式会社東芝 半導体記憶装置およびその製造方法
US6242298B1 (en) 1997-08-29 2001-06-05 Kabushiki Kaisha Toshiba Semiconductor memory device having epitaxial planar capacitor and method for manufacturing the same
JP4439020B2 (ja) 1998-03-26 2010-03-24 株式会社東芝 半導体記憶装置及びその製造方法
US6137128A (en) * 1998-06-09 2000-10-24 International Business Machines Corporation Self-isolated and self-aligned 4F-square vertical fet-trench dram cells
JP3743189B2 (ja) * 1999-01-27 2006-02-08 富士通株式会社 不揮発性半導体記憶装置及びその製造方法

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Publication number Publication date
JP2002026279A (ja) 2002-01-25
US6544833B2 (en) 2003-04-08
US20020004249A1 (en) 2002-01-10

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