JP2002026279A5 - - Google Patents

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Publication number
JP2002026279A5
JP2002026279A5 JP2000199935A JP2000199935A JP2002026279A5 JP 2002026279 A5 JP2002026279 A5 JP 2002026279A5 JP 2000199935 A JP2000199935 A JP 2000199935A JP 2000199935 A JP2000199935 A JP 2000199935A JP 2002026279 A5 JP2002026279 A5 JP 2002026279A5
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JP
Japan
Prior art keywords
forming
crystal semiconductor
single crystal
pillars
semiconductor layer
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Application number
JP2000199935A
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English (en)
Japanese (ja)
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JP2002026279A (ja
JP3655175B2 (ja
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Priority to JP2000199935A priority Critical patent/JP3655175B2/ja
Priority claimed from JP2000199935A external-priority patent/JP3655175B2/ja
Priority to US09/893,664 priority patent/US6544833B2/en
Publication of JP2002026279A publication Critical patent/JP2002026279A/ja
Publication of JP2002026279A5 publication Critical patent/JP2002026279A5/ja
Application granted granted Critical
Publication of JP3655175B2 publication Critical patent/JP3655175B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000199935A 2000-06-30 2000-06-30 半導体記憶装置の製造方法 Expired - Fee Related JP3655175B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000199935A JP3655175B2 (ja) 2000-06-30 2000-06-30 半導体記憶装置の製造方法
US09/893,664 US6544833B2 (en) 2000-06-30 2001-06-29 Semiconductor memory device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000199935A JP3655175B2 (ja) 2000-06-30 2000-06-30 半導体記憶装置の製造方法

Publications (3)

Publication Number Publication Date
JP2002026279A JP2002026279A (ja) 2002-01-25
JP2002026279A5 true JP2002026279A5 (enExample) 2004-10-28
JP3655175B2 JP3655175B2 (ja) 2005-06-02

Family

ID=18697879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000199935A Expired - Fee Related JP3655175B2 (ja) 2000-06-30 2000-06-30 半導体記憶装置の製造方法

Country Status (2)

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US (1) US6544833B2 (enExample)
JP (1) JP3655175B2 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7205604B2 (en) * 2001-03-13 2007-04-17 International Business Machines Corporation Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof
JP2004214544A (ja) * 2003-01-08 2004-07-29 Fujitsu Ltd 半導体装置の製造方法
US6943407B2 (en) * 2003-06-17 2005-09-13 International Business Machines Corporation Low leakage heterojunction vertical transistors and high performance devices thereof
TWI294670B (en) * 2003-06-17 2008-03-11 Ibm Ultra scalable high speed heterojunction vertical n-channel misfets and methods thereof
JP2005108876A (ja) * 2003-09-26 2005-04-21 Toshiba Corp 半導体装置及びその製造方法
US20050070043A1 (en) * 2003-09-30 2005-03-31 Koji Yamakawa Semiconductor device and method for manufacturing the same
KR100560803B1 (ko) * 2004-02-04 2006-03-13 삼성전자주식회사 캐패시터를 갖는 반도체 소자 및 그 제조방법
WO2006043329A1 (ja) * 2004-10-22 2006-04-27 Fujitsu Limited 半導体装置及びその製造方法
JP4795677B2 (ja) * 2004-12-02 2011-10-19 ルネサスエレクトロニクス株式会社 半導体装置およびそれを用いた半導体モジュール、ならびに半導体装置の製造方法
US7326611B2 (en) * 2005-02-03 2008-02-05 Micron Technology, Inc. DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays
JP2006278674A (ja) 2005-03-29 2006-10-12 Nec Electronics Corp 電界効果トランジスタとその製造方法、及び半導体装置
JP2007305747A (ja) * 2006-05-10 2007-11-22 Nec Electronics Corp 半導体装置、及びコンデンサマイクロフォン
KR100971411B1 (ko) * 2008-05-21 2010-07-21 주식회사 하이닉스반도체 반도체 장치의 수직 채널 트랜지스터 형성 방법
JP2010129972A (ja) 2008-12-01 2010-06-10 Elpida Memory Inc 半導体装置およびその製造方法
TWI455291B (zh) * 2009-10-30 2014-10-01 Inotera Memories Inc 垂直式電晶體及其製造方法
JP5421317B2 (ja) * 2011-03-24 2014-02-19 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US9478736B2 (en) * 2013-03-15 2016-10-25 International Business Machines Corporation Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns
DE102015206175A1 (de) * 2015-04-07 2016-10-13 Globalfoundries Inc. Halbleiterbauelement mit Dünnschicht-Widerstand
KR102783332B1 (ko) * 2019-12-24 2025-03-20 삼성전자주식회사 반도체 소자 및 그의 제조 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5691219A (en) 1994-09-17 1997-11-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor memory device
US5739563A (en) 1995-03-15 1998-04-14 Kabushiki Kaisha Toshiba Ferroelectric type semiconductor device having a barium titanate type dielectric film and method for manufacturing the same
DE19637389C1 (de) * 1996-09-13 1997-10-16 Siemens Ag Verfahren zur Herstellung einer DRAM-Zellenanordnung
US5990509A (en) * 1997-01-22 1999-11-23 International Business Machines Corporation 2F-square memory cell for gigabit memory applications
EP0899790A3 (de) * 1997-08-27 2006-02-08 Infineon Technologies AG DRAM-Zellanordnung und Verfahren zu deren Herstellung
JP3311276B2 (ja) 1997-08-29 2002-08-05 株式会社東芝 半導体記憶装置およびその製造方法
US6242298B1 (en) 1997-08-29 2001-06-05 Kabushiki Kaisha Toshiba Semiconductor memory device having epitaxial planar capacitor and method for manufacturing the same
JP4439020B2 (ja) 1998-03-26 2010-03-24 株式会社東芝 半導体記憶装置及びその製造方法
US6137128A (en) * 1998-06-09 2000-10-24 International Business Machines Corporation Self-isolated and self-aligned 4F-square vertical fet-trench dram cells
JP3743189B2 (ja) * 1999-01-27 2006-02-08 富士通株式会社 不揮発性半導体記憶装置及びその製造方法

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