JP3403551B2 - クロック分配回路 - Google Patents

クロック分配回路

Info

Publication number
JP3403551B2
JP3403551B2 JP17908195A JP17908195A JP3403551B2 JP 3403551 B2 JP3403551 B2 JP 3403551B2 JP 17908195 A JP17908195 A JP 17908195A JP 17908195 A JP17908195 A JP 17908195A JP 3403551 B2 JP3403551 B2 JP 3403551B2
Authority
JP
Japan
Prior art keywords
clock
circuit
output
voltage
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP17908195A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0934584A (ja
Inventor
聡 田野井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP17908195A priority Critical patent/JP3403551B2/ja
Priority to DE69633539T priority patent/DE69633539T2/de
Priority to EP96305040A priority patent/EP0753808B1/en
Priority to TW085108431A priority patent/TW301823B/zh
Priority to KR1019960028601A priority patent/KR100290592B1/ko
Priority to US08/678,860 priority patent/US5751665A/en
Publication of JPH0934584A publication Critical patent/JPH0934584A/ja
Application granted granted Critical
Publication of JP3403551B2 publication Critical patent/JP3403551B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
JP17908195A 1995-07-05 1995-07-14 クロック分配回路 Expired - Fee Related JP3403551B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP17908195A JP3403551B2 (ja) 1995-07-14 1995-07-14 クロック分配回路
DE69633539T DE69633539T2 (de) 1995-07-14 1996-07-09 Taktverteilungsschaltung
EP96305040A EP0753808B1 (en) 1995-07-14 1996-07-09 Clock distributing circuit
TW085108431A TW301823B (OSRAM) 1995-07-14 1996-07-11
KR1019960028601A KR100290592B1 (ko) 1995-07-05 1996-07-15 클럭분배회로
US08/678,860 US5751665A (en) 1995-07-14 1996-07-21 Clock distributing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17908195A JP3403551B2 (ja) 1995-07-14 1995-07-14 クロック分配回路

Publications (2)

Publication Number Publication Date
JPH0934584A JPH0934584A (ja) 1997-02-07
JP3403551B2 true JP3403551B2 (ja) 2003-05-06

Family

ID=16059759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17908195A Expired - Fee Related JP3403551B2 (ja) 1995-07-05 1995-07-14 クロック分配回路

Country Status (5)

Country Link
US (1) US5751665A (OSRAM)
EP (1) EP0753808B1 (OSRAM)
JP (1) JP3403551B2 (OSRAM)
DE (1) DE69633539T2 (OSRAM)
TW (1) TW301823B (OSRAM)

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DE19627634C1 (de) * 1996-07-09 1997-07-24 Siemens Ag CMOS-Schaltung aus CMOS-Schaltungsblöcken, die in bitparallelen Datenpfaden angeordnet sind
US6115318A (en) 1996-12-03 2000-09-05 Micron Technology, Inc. Clock vernier adjustment
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US5920518A (en) 1997-02-11 1999-07-06 Micron Technology, Inc. Synchronous clock generator including delay-locked loop
US6912680B1 (en) 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US5907589A (en) * 1997-04-10 1999-05-25 Motorola, Inc. GHZ range frequency divider in CMOS
US6173432B1 (en) * 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US5983013A (en) * 1997-06-30 1999-11-09 Sun Microsystems, Inc. Method for generating non-blocking delayed clocking signals for domino logic
US5953284A (en) 1997-07-09 1999-09-14 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
US6011732A (en) 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
US5926047A (en) 1997-08-29 1999-07-20 Micron Technology, Inc. Synchronous clock generator including a delay-locked loop signal loss detector
US5940609A (en) * 1997-08-29 1999-08-17 Micorn Technology, Inc. Synchronous clock generator including a false lock detector
US6101197A (en) 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
KR100269316B1 (ko) * 1997-12-02 2000-10-16 윤종용 동기지연회로가결합된지연동기루프(dll)및위상동기루프(pll)
US5867453A (en) * 1998-02-06 1999-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Self-setup non-overlap clock generator
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US6016282A (en) 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6349399B1 (en) * 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6029250A (en) 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6118314A (en) * 1998-10-14 2000-09-12 Vlsi Technology, Inc. Circuit assembly and method of synchronizing plural circuits
JP3753355B2 (ja) 1998-11-10 2006-03-08 株式会社ルネサステクノロジ 半導体装置
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6717997B1 (en) * 1998-12-01 2004-04-06 International Business Machines Corporation Apparatus and method for current demand distribution in electronic systems
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US6594772B1 (en) * 2000-01-14 2003-07-15 Hewlett-Packard Development Company, L.P. Clock distribution circuitry to different nodes on integrated circuit with clock coupling circuitry to maintain predetermined phase relation between output and input of adjacent nodes
US6513149B1 (en) 2000-03-31 2003-01-28 International Business Machines Corporation Routing balanced clock signals
US6566921B1 (en) * 2000-08-03 2003-05-20 International Business Machines Corporation Apparatus and method for high resolution frequency adjustment in a multistage frequency synthesizer
US6963992B1 (en) * 2000-09-28 2005-11-08 Cypress Semiconductor Corp. Method and apparatus to generate clock and control signals for over-clocking recovery in a PLL
US6760277B1 (en) * 2001-04-06 2004-07-06 Advanced Micro Devices, Inc. Arrangement for generating multiple clocks in field programmable gate arrays of a network test system
US6801989B2 (en) * 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US6566924B2 (en) * 2001-07-25 2003-05-20 Hewlett-Packard Development Company L.P. Parallel push algorithm detecting constraints to minimize clock skew
US6897699B1 (en) * 2002-07-19 2005-05-24 Rambus Inc. Clock distribution network with process, supply-voltage, and temperature compensation
US7256633B1 (en) 2003-05-01 2007-08-14 Ample Communications, Inc. Systems for implementing high speed and high integration chips
US6927615B2 (en) * 2003-06-05 2005-08-09 International Business Machines Corporation Low skew, power efficient local clock signal generation system
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
US6956415B2 (en) * 2003-11-19 2005-10-18 International Business Machines Corporation Modular DLL architecture for generating multiple timings
US6952127B2 (en) * 2003-11-21 2005-10-04 Micron Technology, Inc. Digital phase mixers with enhanced speed
US6982578B2 (en) * 2003-11-26 2006-01-03 Micron Technology, Inc. Digital delay-locked loop circuits with hierarchical delay adjustment
US6982579B2 (en) * 2003-12-11 2006-01-03 Micron Technology, Inc. Digital frequency-multiplying DLLs
US7009434B2 (en) * 2003-12-12 2006-03-07 Micron Technology, Inc. Generating multi-phase clock signals using hierarchical delays
US7528638B2 (en) * 2003-12-22 2009-05-05 Micron Technology, Inc. Clock signal distribution with reduced parasitic loading effects
US7274236B2 (en) * 2005-04-15 2007-09-25 Micron Technology, Inc. Variable delay line with multiple hierarchy
US7368961B2 (en) * 2005-12-22 2008-05-06 Rambus Inc. Clock distribution network supporting low-power mode
US7882384B2 (en) * 2006-08-31 2011-02-01 National Semiconductor Corporation Setting and minimizing a derived clock frequency based on an input time interval
JP5321179B2 (ja) * 2008-04-11 2013-10-23 富士通株式会社 位相制御装置、位相制御プリント板、制御方法
JP5387187B2 (ja) 2009-07-10 2014-01-15 富士通株式会社 クロック信号分配装置
US9160349B2 (en) * 2009-08-27 2015-10-13 Micron Technology, Inc. Die location compensation
US8610474B2 (en) 2009-10-15 2013-12-17 Rambus Inc. Signal distribution networks and related methods
EP2902866B1 (en) * 2014-02-04 2018-03-07 Hittite Microwave LLC System ready in a clock distribution chip
CN117348687B (zh) * 2023-12-06 2024-03-01 爱科微半导体(上海)有限公司 一种时钟电源杂散优化系统及其校准、标定及优化方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5570054A (en) 1994-09-26 1996-10-29 Hitachi Micro Systems, Inc. Method and apparatus for adaptive clock deskewing

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US5184027A (en) * 1987-03-20 1993-02-02 Hitachi, Ltd. Clock signal supply system
IL89120A (en) * 1988-02-17 1992-08-18 Mips Computer Systems Inc Circuit synchronization system
US5087829A (en) * 1988-12-07 1992-02-11 Hitachi, Ltd. High speed clock distribution system
US5305451A (en) * 1990-09-05 1994-04-19 International Business Machines Corporation Single phase clock distribution circuit for providing clock signals to multiple chip integrated circuit systems
JPH04373009A (ja) * 1991-06-21 1992-12-25 Hitachi Ltd クロック信号の位相調整方法及び電子装置
US5298866A (en) * 1992-06-04 1994-03-29 Kaplinsky Cecil H Clock distribution circuit with active de-skewing
KR100293596B1 (ko) * 1993-01-27 2001-09-17 가나이 쓰도무 Lsi내클럭분배회로

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5570054A (en) 1994-09-26 1996-10-29 Hitachi Micro Systems, Inc. Method and apparatus for adaptive clock deskewing

Also Published As

Publication number Publication date
TW301823B (OSRAM) 1997-04-01
DE69633539T2 (de) 2005-01-27
EP0753808A2 (en) 1997-01-15
DE69633539D1 (de) 2004-11-11
EP0753808A3 (en) 1998-05-13
JPH0934584A (ja) 1997-02-07
US5751665A (en) 1998-05-12
EP0753808B1 (en) 2004-10-06

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