JP3364244B2 - 半導体メモリ装置の製造方法 - Google Patents

半導体メモリ装置の製造方法

Info

Publication number
JP3364244B2
JP3364244B2 JP23764192A JP23764192A JP3364244B2 JP 3364244 B2 JP3364244 B2 JP 3364244B2 JP 23764192 A JP23764192 A JP 23764192A JP 23764192 A JP23764192 A JP 23764192A JP 3364244 B2 JP3364244 B2 JP 3364244B2
Authority
JP
Japan
Prior art keywords
insulator
forming
bit line
capacitor
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP23764192A
Other languages
English (en)
Japanese (ja)
Other versions
JPH05226604A (ja
Inventor
フン・ホ
ゼ・スン・ゾン
Original Assignee
エルジイ・セミコン・カンパニイ・リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019910014048A external-priority patent/KR940005895B1/ko
Priority claimed from KR1019910018278A external-priority patent/KR0124566B1/ko
Application filed by エルジイ・セミコン・カンパニイ・リミテッド filed Critical エルジイ・セミコン・カンパニイ・リミテッド
Publication of JPH05226604A publication Critical patent/JPH05226604A/ja
Application granted granted Critical
Publication of JP3364244B2 publication Critical patent/JP3364244B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP23764192A 1991-08-14 1992-08-14 半導体メモリ装置の製造方法 Expired - Fee Related JP3364244B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR14048/1991 1991-08-14
KR1019910014048A KR940005895B1 (ko) 1991-08-14 1991-08-14 디램 셀의 구조 및 제조방법
KR18278/1991 1991-10-17
KR1019910018278A KR0124566B1 (ko) 1991-10-17 1991-10-17 디램셀의 제조방법

Publications (2)

Publication Number Publication Date
JPH05226604A JPH05226604A (ja) 1993-09-03
JP3364244B2 true JP3364244B2 (ja) 2003-01-08

Family

ID=26628705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23764192A Expired - Fee Related JP3364244B2 (ja) 1991-08-14 1992-08-14 半導体メモリ装置の製造方法

Country Status (4)

Country Link
US (1) US5272102A (enExample)
JP (1) JP3364244B2 (enExample)
DE (1) DE4226996A1 (enExample)
TW (1) TW313677B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384277A (en) * 1993-12-17 1995-01-24 International Business Machines Corporation Method for forming a DRAM trench cell capacitor having a strap connection
US5369049A (en) * 1993-12-17 1994-11-29 International Business Machines Corporation DRAM cell having raised source, drain and isolation
US5451809A (en) * 1994-09-07 1995-09-19 Kabushiki Kaisha Toshiba Smooth surface doped silicon film formation
KR100206885B1 (ko) * 1995-12-30 1999-07-01 구본준 트렌치 캐패시터 메모리셀 제조방법
DE19620625C1 (de) * 1996-05-22 1997-10-23 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
US6570207B2 (en) 2000-12-13 2003-05-27 International Business Machines Corporation Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex
TWI455291B (zh) * 2009-10-30 2014-10-01 Inotera Memories Inc 垂直式電晶體及其製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60261165A (ja) * 1984-06-08 1985-12-24 Hitachi Ltd Ｍｏｓダイナミツクメモリ素子
US4713678A (en) * 1984-12-07 1987-12-15 Texas Instruments Incorporated dRAM cell and method
US4649625A (en) * 1985-10-21 1987-03-17 International Business Machines Corporation Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor
US4816884A (en) * 1987-07-20 1989-03-28 International Business Machines Corporation High density vertical trench transistor and capacitor memory cell structure and fabrication method therefor
US4833516A (en) * 1987-08-03 1989-05-23 International Business Machines Corporation High density memory cell structure having a vertical trench transistor self-aligned with a vertical trench capacitor and fabrication methods therefor
US4988637A (en) * 1990-06-29 1991-01-29 International Business Machines Corp. Method for fabricating a mesa transistor-trench capacitor memory cell structure
US5013680A (en) * 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography

Also Published As

Publication number Publication date
US5272102A (en) 1993-12-21
TW313677B (enExample) 1997-08-21
JPH05226604A (ja) 1993-09-03
DE4226996A1 (de) 1993-02-18

Similar Documents

Publication Publication Date Title
US5336912A (en) Buried plate type DRAM
JP3671062B2 (ja) 半導体装置及びその製造方法
EP0300157B1 (en) Vertical transistor capacitor memory cell structure and fabrication method therefor
US6849496B2 (en) DRAM with vertical transistor and trench capacitor memory cells and method of fabrication
US5436186A (en) Process for fabricating a stacked capacitor
EP0430404B1 (en) Method of manufacturing a capacitor for a DRAM cell
US5843820A (en) Method of fabricating a new dynamic random access memory (DRAM) cell having a buried horizontal trench capacitor
KR100437551B1 (ko) 디램(dram)셀및그제조방법
KR940006679B1 (ko) 수직형 트랜지스터를 갖는 dram셀 및 그 제조방법
KR100445308B1 (ko) 트렌치 커패시터 및 선택 트랜지스터를 구비한 메모리 및그 제조 방법
KR19980063505A (ko) 트렌치 캐패시터 및 그의 형성 방법과, 디램 저장 셀 형성 방법
US5064777A (en) Fabrication method for a double trench memory cell device
JP2000156482A (ja) 半導体メモリ装置及びその製造方法
US5034787A (en) Structure and fabrication method for a double trench memory cell device
US6489646B1 (en) DRAM cells with buried trench capacitors
JP2932540B2 (ja) 半導体メモリ装置
US4694561A (en) Method of making high-performance trench capacitors for DRAM cells
US6638815B1 (en) Formation of self-aligned vertical connector
JP3364244B2 (ja) 半導体メモリ装置の製造方法
US6037209A (en) Method for producing a DRAM cellular arrangement
US5166090A (en) Method for manufacturing a semiconductor random access memory cell
JP2894361B2 (ja) 半導体装置およびその製造方法
JP2000058790A (ja) 半導体装置およびその製造方法
JPH0595091A (ja) 集積回路メモリ用トレンチキヤパシタ及びこれを用いたメモリセルの形成方法
JPH0563155A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees