JP3262250B2 - 現状態/次状態レジスタの効率的利用 - Google Patents
現状態/次状態レジスタの効率的利用Info
- Publication number
- JP3262250B2 JP3262250B2 JP27963594A JP27963594A JP3262250B2 JP 3262250 B2 JP3262250 B2 JP 3262250B2 JP 27963594 A JP27963594 A JP 27963594A JP 27963594 A JP27963594 A JP 27963594A JP 3262250 B2 JP3262250 B2 JP 3262250B2
- Authority
- JP
- Japan
- Prior art keywords
- cost
- array
- accumulated
- accumulated cost
- candidate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4138—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
- H03M13/4146—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3961—Arrangements of methods for branch or transition metric calculation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
- H03M13/6505—Memory efficient implementations
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
- Dc Digital Transmission (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US153334 | 1993-11-16 | ||
| US08/153,334 US5465275A (en) | 1993-11-16 | 1993-11-16 | Efficient utilization of present state/next state registers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07191868A JPH07191868A (ja) | 1995-07-28 |
| JP3262250B2 true JP3262250B2 (ja) | 2002-03-04 |
Family
ID=22546761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27963594A Expired - Fee Related JP3262250B2 (ja) | 1993-11-16 | 1994-11-15 | 現状態/次状態レジスタの効率的利用 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5465275A (enExample) |
| EP (1) | EP0653849A3 (enExample) |
| JP (1) | JP3262250B2 (enExample) |
| KR (1) | KR950016018A (enExample) |
| TW (1) | TW271518B (enExample) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2718865B1 (fr) * | 1994-04-15 | 1996-07-19 | Texas Instruments France | Procédé et dispositif à processeur de signaux numériques pour la mise en Óoeuvre d'un algorithme de Viterbi. |
| FR2724273B1 (fr) * | 1994-09-05 | 1997-01-03 | Sgs Thomson Microelectronics | Circuit de traitement de signal pour mettre en oeuvre un algorithme de viterbi |
| US5619514A (en) * | 1994-12-29 | 1997-04-08 | Lucent Technologies Inc. | In-place present state/next state registers |
| JP3171772B2 (ja) * | 1995-08-23 | 2001-06-04 | 沖電気工業株式会社 | ビタビ復号方法及びビタビ復号装置 |
| EP0782358A3 (en) | 1995-12-29 | 1999-07-21 | Lucent Technologies Inc. | Mobile communicator |
| JPH09232973A (ja) * | 1996-02-28 | 1997-09-05 | Sony Corp | ビタビ復号器 |
| US5742622A (en) * | 1996-03-12 | 1998-04-21 | Discovision Associates | Error detection and correction system for a stream of encoded data |
| US5802116A (en) * | 1996-04-04 | 1998-09-01 | Lucent Technologies Inc. | Soft decision Viterbi decoding with large constraint lengths |
| GB9622540D0 (en) * | 1996-10-30 | 1997-01-08 | Discovision Ass | Trackback for viterbi decoder |
| US6522696B1 (en) | 1997-04-11 | 2003-02-18 | Agere Systems Inc. | Adaptive frequency correction in a wireless communications system, such as for GSM and IS54 |
| KR100484127B1 (ko) * | 1997-08-07 | 2005-06-16 | 삼성전자주식회사 | 비터비디코더 |
| US6009128A (en) * | 1997-09-08 | 1999-12-28 | Lucent Technologies, Inc. | Metric acceleration on dual MAC processor |
| US6530059B1 (en) * | 1998-06-01 | 2003-03-04 | Her Majesty The Queen In Right Of Canada, As Represented By The Minister Of Industry Through The Communication Research Centre | Tail-biting turbo-code encoder and associated decoder |
| JP4071879B2 (ja) * | 1998-12-09 | 2008-04-02 | 富士通株式会社 | 誤り検出器、この誤り検出器を備えた通信システム、および誤り検出方法 |
| KR100331562B1 (ko) | 1999-11-29 | 2002-04-06 | 윤종용 | 지연 동기 루프 회로 및 내부 클럭 신호 발생 방법 |
| US6591395B1 (en) * | 2000-06-18 | 2003-07-08 | Silicon Integrated Systems Corporation | Memory reduction techniques in a viterbi decoder |
| US7020830B2 (en) * | 2001-12-24 | 2006-03-28 | Agere Systems Inc. | High speed add-compare-select operations for use in viterbi decoders |
| TWI228654B (en) * | 2003-07-11 | 2005-03-01 | Mediatek Inc | Non-binary Viterbi data processing system and method |
| US20080152044A1 (en) * | 2006-12-20 | 2008-06-26 | Media Tek Inc. | Veterbi decoding method for convolutionally encoded signal |
| US11367500B2 (en) | 2019-12-20 | 2022-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for LUT-free memory repair |
| DE102020120488A1 (de) * | 2019-12-20 | 2021-06-24 | Taiwan Semiconductor Manufacturing Co. Ltd. | Verfahren zur nachschlagtabellenfreien speicherreperatur |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NZ198844A (en) * | 1980-11-14 | 1984-05-31 | Plessey Overseas | Digital information transmission: two dimensional code |
| GB8315363D0 (en) * | 1983-06-03 | 1983-07-06 | Gordon J A | Decoding errorcorrecting codes |
| US4583078A (en) * | 1984-11-13 | 1986-04-15 | Communications Satellite Corporation | Serial Viterbi decoder |
| US4868830A (en) * | 1985-09-27 | 1989-09-19 | California Institute Of Technology | Method and apparatus for implementing a traceback maximum-likelihood decoder in a hypercube network |
| US4748626A (en) * | 1987-01-28 | 1988-05-31 | Racal Data Communications Inc. | Viterbi decoder with reduced number of data move operations |
| US4979175A (en) * | 1988-07-05 | 1990-12-18 | Motorola, Inc. | State metric memory arrangement for a viterbi decoder |
| FR2669445B1 (fr) * | 1990-11-15 | 1993-01-08 | Alcatel Radiotelephone | Dispositif prevu pour le traitement de l'algorithme de viterbi comprenant un processeur et un operateur specialise. |
| KR930004862B1 (ko) * | 1990-12-17 | 1993-06-09 | 삼성전자 주식회사 | 상태 평가량 기억장치 |
| BE1004814A3 (nl) * | 1991-05-08 | 1993-02-02 | Bell Telephone Mfg | Decodeerinrichting. |
| JP2917577B2 (ja) * | 1991-05-30 | 1999-07-12 | 松下電器産業株式会社 | 演算装置 |
| JP3120511B2 (ja) * | 1991-11-21 | 2000-12-25 | ソニー株式会社 | ビタビ復号装置 |
-
1993
- 1993-11-16 US US08/153,334 patent/US5465275A/en not_active Expired - Lifetime
- 1993-12-06 TW TW082110304A patent/TW271518B/zh not_active IP Right Cessation
-
1994
- 1994-11-09 EP EP94308241A patent/EP0653849A3/en not_active Withdrawn
- 1994-11-15 KR KR1019940029898A patent/KR950016018A/ko not_active Abandoned
- 1994-11-15 JP JP27963594A patent/JP3262250B2/ja not_active Expired - Fee Related
-
1995
- 1995-06-07 US US08/488,274 patent/US5559837A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5559837A (en) | 1996-09-24 |
| US5465275A (en) | 1995-11-07 |
| KR950016018A (ko) | 1995-06-17 |
| EP0653849A2 (en) | 1995-05-17 |
| JPH07191868A (ja) | 1995-07-28 |
| TW271518B (enExample) | 1996-03-01 |
| EP0653849A3 (en) | 1997-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3262250B2 (ja) | 現状態/次状態レジスタの効率的利用 | |
| JP3241210B2 (ja) | ビタビ復号方法及びビタビ復号回路 | |
| JP3747604B2 (ja) | ビタビ復号装置 | |
| US4979175A (en) | State metric memory arrangement for a viterbi decoder | |
| US5619514A (en) | In-place present state/next state registers | |
| US20030099140A1 (en) | Data handling system | |
| KR20070064678A (ko) | Map 디코더용 파이프라인 구조 | |
| JPH09153822A (ja) | データ処理システムにおける加算比較選択バタフライ演算およびその命令を実行する方法 | |
| KR920005739B1 (ko) | 기억부(memoryunit)에 사용되는 부분기입 제어회로. | |
| JPH03501660A (ja) | 記憶装置への部分書き込み操作における誤り検出 | |
| JPH07212336A (ja) | 減少長トレースバック | |
| CN100550657C (zh) | 维特比译码装置 | |
| WO2000010089A1 (en) | Content addressable memory addressable by redundant form input data | |
| JP2004046593A (ja) | キャッシュメモリ及びその制御方法 | |
| JP3260714B2 (ja) | ビタビ復号化装置およびビタビ復号化方法 | |
| HK1005007A (en) | Efficient utilization of present state/next state registers | |
| HK1006378A (en) | In-place present state/next state registers | |
| JP2571384B2 (ja) | シ−ケンシャル復号器 | |
| KR0183115B1 (ko) | 비터비 디코더의 패스 메모리의 제어회로 | |
| JPH02217918A (ja) | メモリインタフェース回路 | |
| JPH11186915A (ja) | ビタビ復号装置 | |
| CN101160729B (zh) | 用于并行处理递归数据的定址体系结构 | |
| JPH04100324A (ja) | 可変長符号の復号方式 | |
| JPS63129714A (ja) | ビタビ復号器 | |
| JPS59114936A (ja) | 復号器 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20011114 |
|
| LAPS | Cancellation because of no payment of annual fees |