JP2718647B2 - 積層半導体パッケージ - Google Patents

積層半導体パッケージ

Info

Publication number
JP2718647B2
JP2718647B2 JP7143114A JP14311495A JP2718647B2 JP 2718647 B2 JP2718647 B2 JP 2718647B2 JP 7143114 A JP7143114 A JP 7143114A JP 14311495 A JP14311495 A JP 14311495A JP 2718647 B2 JP2718647 B2 JP 2718647B2
Authority
JP
Japan
Prior art keywords
semiconductor package
semiconductor chip
electrically connected
leads
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7143114A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0851127A (ja
Inventor
寧 度 權
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH0851127A publication Critical patent/JPH0851127A/ja
Application granted granted Critical
Publication of JP2718647B2 publication Critical patent/JP2718647B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10W76/10—
    • H10W72/00—
    • H10W90/00—
    • H10W70/40—
    • H10W70/60—
    • H10W74/00—

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP7143114A 1994-06-09 1995-06-09 積層半導体パッケージ Expired - Fee Related JP2718647B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019940012951A KR0134648B1 (ko) 1994-06-09 1994-06-09 노이즈가 적은 적층 멀티칩 패키지
KR1994-12951 1994-06-09

Publications (2)

Publication Number Publication Date
JPH0851127A JPH0851127A (ja) 1996-02-20
JP2718647B2 true JP2718647B2 (ja) 1998-02-25

Family

ID=19384966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7143114A Expired - Fee Related JP2718647B2 (ja) 1994-06-09 1995-06-09 積層半導体パッケージ

Country Status (4)

Country Link
US (1) US5656856A (enExample)
JP (1) JP2718647B2 (enExample)
KR (1) KR0134648B1 (enExample)
TW (1) TW275137B (enExample)

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JP4233776B2 (ja) * 2001-09-12 2009-03-04 株式会社村田製作所 回路形成基板
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JP4424351B2 (ja) * 2004-09-08 2010-03-03 パナソニック株式会社 立体的電子回路装置の製造方法
KR100658734B1 (ko) * 2004-11-11 2006-12-19 주식회사 유니세미콘 스택 패키지 및 그 제조방법
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CN100552940C (zh) * 2005-11-25 2009-10-21 全懋精密科技股份有限公司 半导体元件埋入承载板的叠接结构
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US7863189B2 (en) * 2007-01-05 2011-01-04 International Business Machines Corporation Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density
US20080284037A1 (en) 2007-05-15 2008-11-20 Andry Paul S Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers
KR100909764B1 (ko) 2007-10-31 2009-07-29 주식회사 하이닉스반도체 반도체 소자의 형성 방법
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CN101465341B (zh) * 2007-12-21 2011-07-06 南亚科技股份有限公司 堆叠式芯片封装结构
US8063474B2 (en) * 2008-02-06 2011-11-22 Fairchild Semiconductor Corporation Embedded die package on package (POP) with pre-molded leadframe
CN102101490B (zh) 2009-12-18 2014-07-16 明门香港股份有限公司 可收合式婴幼儿承载装置
CN102101489B (zh) 2009-12-18 2013-07-03 明门香港股份有限公司 具可调整推杆的婴儿承载装置
US8827283B2 (en) * 2010-04-01 2014-09-09 Nuna International B.V. Mounting system and method of installing a child support accessory on a stroller frame
US8803262B2 (en) * 2012-01-17 2014-08-12 Rosemount Aerospace Inc. Die attach stress isolation
CN103779351B (zh) * 2012-10-23 2017-11-07 格科微电子（上海）有限公司 三维封装结构及其制造方法
US9620473B1 (en) 2013-01-18 2017-04-11 University Of Notre Dame Du Lac Quilt packaging system with interdigitated interconnecting nodules for inter-chip alignment
KR102099878B1 (ko) * 2013-07-11 2020-04-10 삼성전자 주식회사 반도체 패키지
KR102245770B1 (ko) 2013-10-29 2021-04-28 삼성전자주식회사 반도체 패키지 장치
US10204737B2 (en) 2014-06-11 2019-02-12 Avx Corporation Low noise capacitors
WO2018063396A1 (en) 2016-09-30 2018-04-05 Intel Corporation Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability
KR102639101B1 (ko) * 2017-02-24 2024-02-22 에스케이하이닉스 주식회사 전자기간섭 차폐 구조를 갖는 반도체 패키지
US10741466B2 (en) * 2017-11-17 2020-08-11 Infineon Technologies Ag Formation of conductive connection tracks in package mold body using electroless plating
US11133281B2 (en) 2019-04-04 2021-09-28 Infineon Technologies Ag Chip to chip interconnect in encapsulant of molded semiconductor package
CN112018052A (zh) 2019-05-31 2020-12-01 英飞凌科技奥地利有限公司 具有可激光活化模制化合物的半导体封装
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Also Published As

Publication number Publication date
KR960002762A (ko) 1996-01-26
TW275137B (enExample) 1996-05-01
KR0134648B1 (ko) 1998-04-20
JPH0851127A (ja) 1996-02-20
US5656856A (en) 1997-08-12

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