JP2662144B2 - 集積回路 - Google Patents

集積回路

Info

Publication number
JP2662144B2
JP2662144B2 JP4147894A JP14789492A JP2662144B2 JP 2662144 B2 JP2662144 B2 JP 2662144B2 JP 4147894 A JP4147894 A JP 4147894A JP 14789492 A JP14789492 A JP 14789492A JP 2662144 B2 JP2662144 B2 JP 2662144B2
Authority
JP
Japan
Prior art keywords
pull
gate
down transistor
region
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4147894A
Other languages
English (en)
Japanese (ja)
Other versions
JPH05160369A (ja
Inventor
リー クォーファ
ジョン ナジー ウィリアム
サン ジャンミー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of JPH05160369A publication Critical patent/JPH05160369A/ja
Application granted granted Critical
Publication of JP2662144B2 publication Critical patent/JP2662144B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element

Landscapes

  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP4147894A 1991-05-16 1992-05-15 集積回路 Expired - Lifetime JP2662144B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/701,270 US5128738A (en) 1991-05-16 1991-05-16 Integrated circuit
US701270 1996-08-22

Publications (2)

Publication Number Publication Date
JPH05160369A JPH05160369A (ja) 1993-06-25
JP2662144B2 true JP2662144B2 (ja) 1997-10-08

Family

ID=24816679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4147894A Expired - Lifetime JP2662144B2 (ja) 1991-05-16 1992-05-15 集積回路

Country Status (7)

Country Link
US (1) US5128738A (ref)
EP (1) EP0514095B1 (ref)
JP (1) JP2662144B2 (ref)
KR (1) KR100257953B1 (ref)
DE (1) DE69222973T2 (ref)
ES (1) ES2109311T3 (ref)
TW (1) TW198131B (ref)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5213990A (en) * 1992-04-01 1993-05-25 Texas Instruments, Incorporated Method for forming a stacked semiconductor structure
JPH05283654A (ja) * 1992-04-03 1993-10-29 Toshiba Corp マスクｒｏｍとその製造方法
US5721445A (en) * 1995-03-02 1998-02-24 Lucent Technologies Inc. Semiconductor device with increased parasitic emitter resistance and improved latch-up immunity
US5631112A (en) * 1995-11-16 1997-05-20 Vanguard International Semiconductor Corporation Multiple exposure method for photo-exposing photosensitive layers upon high step height topography substrate layers
US5707765A (en) * 1996-05-28 1998-01-13 Microunity Systems Engineering, Inc. Photolithography mask using serifs and method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5736844A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Semiconductor device
JPS59201461A (ja) * 1983-04-28 1984-11-15 Toshiba Corp 読み出し専用半導体記憶装置およびその製造方法
JPS59231851A (ja) * 1983-06-14 1984-12-26 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリセル
JPH0628302B2 (ja) * 1984-02-28 1994-04-13 富士通株式会社 半導体記憶装置
JPS63126270A (ja) * 1986-11-14 1988-05-30 Mitsubishi Electric Corp 半導体記憶装置
JPH0831533B2 (ja) * 1988-10-21 1996-03-27 セイコーエプソン株式会社 半導体記憶装置
WO1989011162A1 (fr) * 1988-05-07 1989-11-16 Seiko Epson Corporation Dispositif a semi-conducteurs et memoire a semi-conducteurs
JPH0735399Y2 (ja) * 1989-05-12 1995-08-09 ソニー株式会社 半導体メモリ

Also Published As

Publication number Publication date
KR920022535A (ko) 1992-12-19
DE69222973T2 (de) 1998-03-05
US5128738A (en) 1992-07-07
EP0514095B1 (en) 1997-11-05
TW198131B (ref) 1993-01-11
DE69222973D1 (de) 1997-12-11
ES2109311T3 (es) 1998-01-16
JPH05160369A (ja) 1993-06-25
EP0514095A2 (en) 1992-11-19
KR100257953B1 (ko) 2000-06-01
EP0514095A3 (en) 1992-12-30

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