ES2109311T3 - Circuito integrado que utiliza celulas sram. - Google Patents
Circuito integrado que utiliza celulas sram.Info
- Publication number
- ES2109311T3 ES2109311T3 ES92304178T ES92304178T ES2109311T3 ES 2109311 T3 ES2109311 T3 ES 2109311T3 ES 92304178 T ES92304178 T ES 92304178T ES 92304178 T ES92304178 T ES 92304178T ES 2109311 T3 ES2109311 T3 ES 2109311T3
- Authority
- ES
- Spain
- Prior art keywords
- integrated circuit
- transistor
- sram cells
- connection
- door
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
UNA CELULA DE MEMORIA SEMICONDUCTORA TIENE UN PUERTA PARALELA (EJEMPLO 25). LA DIRECCION DE LA PUERTA SE ESCOGE VOLUNTARIAMENTE PARA MINIMIZAR LOS EFECTOS ASTIGMATICOS LITOGRAFICOS. ASI SE FABRICAN PUERTAS DE ANCHURA COMPARATIVAMENTE UNIFORME Y SE MEJORA LA PREDICCION DEL RENDIMIENTO DE TRANSISTOR. UNA INCORPORACION DEL INVENTO MUESTRA UNA CONEXION ENTRE DOS CAPAS CONDUCTORAS (35,43) Y UNA FUENTE/DRENAJE (15). LA CONEXION FORMA UN NUDO ENTRE UN TRANSISTOR DE ACCESO Y UN TRANSISTOR DISMINUIDO.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/701,270 US5128738A (en) | 1991-05-16 | 1991-05-16 | Integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2109311T3 true ES2109311T3 (es) | 1998-01-16 |
Family
ID=24816679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES92304178T Expired - Lifetime ES2109311T3 (es) | 1991-05-16 | 1992-05-08 | Circuito integrado que utiliza celulas sram. |
Country Status (7)
Country | Link |
---|---|
US (1) | US5128738A (es) |
EP (1) | EP0514095B1 (es) |
JP (1) | JP2662144B2 (es) |
KR (1) | KR100257953B1 (es) |
DE (1) | DE69222973T2 (es) |
ES (1) | ES2109311T3 (es) |
TW (1) | TW198131B (es) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5213990A (en) * | 1992-04-01 | 1993-05-25 | Texas Instruments, Incorporated | Method for forming a stacked semiconductor structure |
JPH05283654A (ja) * | 1992-04-03 | 1993-10-29 | Toshiba Corp | マスクromとその製造方法 |
US5721445A (en) * | 1995-03-02 | 1998-02-24 | Lucent Technologies Inc. | Semiconductor device with increased parasitic emitter resistance and improved latch-up immunity |
US5631112A (en) * | 1995-11-16 | 1997-05-20 | Vanguard International Semiconductor Corporation | Multiple exposure method for photo-exposing photosensitive layers upon high step height topography substrate layers |
US5707765A (en) * | 1996-05-28 | 1998-01-13 | Microunity Systems Engineering, Inc. | Photolithography mask using serifs and method thereof |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5736844A (en) * | 1980-08-15 | 1982-02-27 | Hitachi Ltd | Semiconductor device |
JPS59201461A (ja) * | 1983-04-28 | 1984-11-15 | Toshiba Corp | 読み出し専用半導体記憶装置およびその製造方法 |
JPS59231851A (ja) * | 1983-06-14 | 1984-12-26 | Nippon Telegr & Teleph Corp <Ntt> | 半導体メモリセル |
JPH0628302B2 (ja) * | 1984-02-28 | 1994-04-13 | 富士通株式会社 | 半導体記憶装置 |
JPS63126270A (ja) * | 1986-11-14 | 1988-05-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH0831533B2 (ja) * | 1988-10-21 | 1996-03-27 | セイコーエプソン株式会社 | 半導体記憶装置 |
WO1989011162A1 (en) * | 1988-05-07 | 1989-11-16 | Seiko Epson Corporation | Semiconductor device and semiconductor memory device |
JPH0735399Y2 (ja) * | 1989-05-12 | 1995-08-09 | ソニー株式会社 | 半導体メモリ |
-
1991
- 1991-05-16 US US07/701,270 patent/US5128738A/en not_active Expired - Lifetime
-
1992
- 1992-04-11 TW TW081102826A patent/TW198131B/zh active
- 1992-05-07 KR KR1019920007690A patent/KR100257953B1/ko not_active IP Right Cessation
- 1992-05-08 EP EP92304178A patent/EP0514095B1/en not_active Expired - Lifetime
- 1992-05-08 ES ES92304178T patent/ES2109311T3/es not_active Expired - Lifetime
- 1992-05-08 DE DE69222973T patent/DE69222973T2/de not_active Expired - Fee Related
- 1992-05-15 JP JP4147894A patent/JP2662144B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2662144B2 (ja) | 1997-10-08 |
DE69222973T2 (de) | 1998-03-05 |
TW198131B (es) | 1993-01-11 |
EP0514095B1 (en) | 1997-11-05 |
KR920022535A (ko) | 1992-12-19 |
DE69222973D1 (de) | 1997-12-11 |
JPH05160369A (ja) | 1993-06-25 |
KR100257953B1 (ko) | 2000-06-01 |
US5128738A (en) | 1992-07-07 |
EP0514095A2 (en) | 1992-11-19 |
EP0514095A3 (en) | 1992-12-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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