JP2535082B2 - 双極性相補形金属酸化物半導体出力駆動回路 - Google Patents
双極性相補形金属酸化物半導体出力駆動回路Info
- Publication number
- JP2535082B2 JP2535082B2 JP2017636A JP1763690A JP2535082B2 JP 2535082 B2 JP2535082 B2 JP 2535082B2 JP 2017636 A JP2017636 A JP 2017636A JP 1763690 A JP1763690 A JP 1763690A JP 2535082 B2 JP2535082 B2 JP 2535082B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- gate
- inverter
- drain
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/303,855 US4933574A (en) | 1989-01-30 | 1989-01-30 | BiCMOS output driver |
US303855 | 1989-01-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02235433A JPH02235433A (ja) | 1990-09-18 |
JP2535082B2 true JP2535082B2 (ja) | 1996-09-18 |
Family
ID=23174005
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017636A Expired - Lifetime JP2535082B2 (ja) | 1989-01-30 | 1990-01-26 | 双極性相補形金属酸化物半導体出力駆動回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4933574A (de) |
EP (1) | EP0380960B1 (de) |
JP (1) | JP2535082B2 (de) |
DE (1) | DE69007640T2 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0683058B2 (ja) * | 1989-10-06 | 1994-10-19 | 株式会社東芝 | 出力回路 |
JPH03158018A (ja) * | 1989-11-15 | 1991-07-08 | Nec Corp | 入力回路 |
US5148047A (en) * | 1990-06-11 | 1992-09-15 | Motorola, Inc. | CMOS bus driver circuit with improved speed |
US5153457A (en) * | 1990-12-12 | 1992-10-06 | Texas Instruments Incorporated | Output buffer with di/dt and dv/dt and tri-state control |
US6208195B1 (en) | 1991-03-18 | 2001-03-27 | Integrated Device Technology, Inc. | Fast transmission gate switch |
WO1992016998A1 (en) | 1991-03-18 | 1992-10-01 | Quality Semiconductor, Inc. | Fast transmission gate switch |
CA2171307C (en) * | 1993-09-16 | 2004-11-23 | Zwie Amitai | Scan test circuit using fast transmission gate switch |
JP3190199B2 (ja) * | 1994-03-16 | 2001-07-23 | 株式会社東芝 | 同相信号出力回路、逆相信号出力回路、二相信号出力回路及び信号出力回路 |
JP3586467B2 (ja) * | 1994-03-25 | 2004-11-10 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Vcc補償されたダイナミック閥値を備えたCMOS入力 |
US5428303A (en) * | 1994-05-20 | 1995-06-27 | National Semiconductor Corporation | Bias generator for low ground bounce output driver |
US5563543A (en) * | 1994-12-14 | 1996-10-08 | Philips Electronics North America Corporation | Low-voltage BiCMOS digital delay chain suitable for operation over a wide power supply range |
WO1997030398A1 (en) * | 1996-02-20 | 1997-08-21 | Intergraph Corporation | Apparatus and method for signal handling on gtl-type buses |
US6307399B1 (en) | 1998-06-02 | 2001-10-23 | Integrated Device Technology, Inc. | High speed buffer circuit with improved noise immunity |
US6329834B1 (en) * | 1999-12-30 | 2001-12-11 | Texas Instruments Incorporated | Reduction of switching noise in integrated circuits |
US6570405B1 (en) | 2001-12-20 | 2003-05-27 | Integrated Device Technology, Inc. | Integrated output driver circuits having current sourcing and current sinking characteristics that inhibit power bounce and ground bounce |
US6894529B1 (en) | 2003-07-09 | 2005-05-17 | Integrated Device Technology, Inc. | Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57166734A (en) * | 1981-04-06 | 1982-10-14 | Matsushita Electric Ind Co Ltd | Electronic circuit |
JPS60125015A (ja) * | 1983-12-12 | 1985-07-04 | Hitachi Ltd | インバ−タ回路 |
JPS61118023A (ja) * | 1984-11-14 | 1986-06-05 | Toshiba Corp | Mos型半導体集積回路の入力ゲ−ト回路 |
JP2544343B2 (ja) * | 1985-02-07 | 1996-10-16 | 株式会社日立製作所 | 半導体集積回路装置 |
EP0209805B1 (de) * | 1985-07-22 | 1993-04-07 | Hitachi, Ltd. | Halbleitereinrichtung mit bipolarem Transistor und Isolierschicht-Feldeffekttransistor |
JPS62169520A (ja) * | 1986-01-22 | 1987-07-25 | Hitachi Ltd | Lsi |
JPS62220026A (ja) * | 1986-03-20 | 1987-09-28 | Toshiba Corp | 出力バツフア回路 |
US4707623A (en) * | 1986-07-29 | 1987-11-17 | Rca Corporation | CMOS input level shifting buffer circuit |
JPS6382122A (ja) * | 1986-09-26 | 1988-04-12 | Toshiba Corp | 論理回路 |
US4785201A (en) * | 1986-12-29 | 1988-11-15 | Integrated Device Technology, Inc. | High speed/high drive CMOS output buffer with inductive bounce suppression |
-
1989
- 1989-01-30 US US07/303,855 patent/US4933574A/en not_active Expired - Lifetime
-
1990
- 1990-01-17 EP EP90100878A patent/EP0380960B1/de not_active Expired - Lifetime
- 1990-01-17 DE DE69007640T patent/DE69007640T2/de not_active Expired - Fee Related
- 1990-01-26 JP JP2017636A patent/JP2535082B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0380960A2 (de) | 1990-08-08 |
DE69007640T2 (de) | 1994-07-14 |
EP0380960A3 (en) | 1990-12-05 |
US4933574A (en) | 1990-06-12 |
DE69007640D1 (de) | 1994-05-05 |
JPH02235433A (ja) | 1990-09-18 |
EP0380960B1 (de) | 1994-03-30 |
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