JP2519651Y2 - 樹脂封止型マルチチップパッケージのリードフレーム - Google Patents

樹脂封止型マルチチップパッケージのリードフレーム

Info

Publication number
JP2519651Y2
JP2519651Y2 JP4757690U JP4757690U JP2519651Y2 JP 2519651 Y2 JP2519651 Y2 JP 2519651Y2 JP 4757690 U JP4757690 U JP 4757690U JP 4757690 U JP4757690 U JP 4757690U JP 2519651 Y2 JP2519651 Y2 JP 2519651Y2
Authority
JP
Japan
Prior art keywords
lead frame
resin
lead
islands
chip package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4757690U
Other languages
English (en)
Japanese (ja)
Other versions
JPH048446U (enrdf_load_stackoverflow
Inventor
秀史 高谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Motor Corp
Original Assignee
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Priority to JP4757690U priority Critical patent/JP2519651Y2/ja
Publication of JPH048446U publication Critical patent/JPH048446U/ja
Application granted granted Critical
Publication of JP2519651Y2 publication Critical patent/JP2519651Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP4757690U 1990-05-07 1990-05-07 樹脂封止型マルチチップパッケージのリードフレーム Expired - Lifetime JP2519651Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4757690U JP2519651Y2 (ja) 1990-05-07 1990-05-07 樹脂封止型マルチチップパッケージのリードフレーム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4757690U JP2519651Y2 (ja) 1990-05-07 1990-05-07 樹脂封止型マルチチップパッケージのリードフレーム

Publications (2)

Publication Number Publication Date
JPH048446U JPH048446U (enrdf_load_stackoverflow) 1992-01-27
JP2519651Y2 true JP2519651Y2 (ja) 1996-12-11

Family

ID=31563627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4757690U Expired - Lifetime JP2519651Y2 (ja) 1990-05-07 1990-05-07 樹脂封止型マルチチップパッケージのリードフレーム

Country Status (1)

Country Link
JP (1) JP2519651Y2 (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008147589A (ja) * 2006-12-13 2008-06-26 Toyota Motor Corp 電子部品
JP5834647B2 (ja) * 2011-09-07 2015-12-24 大日本印刷株式会社 リードフレームおよびその製造方法
WO2019203139A1 (ja) * 2018-04-19 2019-10-24 ローム株式会社 半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010967A (enrdf_load_stackoverflow) * 1973-05-28 1975-02-04
JPH01308058A (ja) * 1988-06-06 1989-12-12 Hitachi Ltd 電子装置

Also Published As

Publication number Publication date
JPH048446U (enrdf_load_stackoverflow) 1992-01-27

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term