JP2024519492A5 - - Google Patents

Info

Publication number
JP2024519492A5
JP2024519492A5 JP2023567953A JP2023567953A JP2024519492A5 JP 2024519492 A5 JP2024519492 A5 JP 2024519492A5 JP 2023567953 A JP2023567953 A JP 2023567953A JP 2023567953 A JP2023567953 A JP 2023567953A JP 2024519492 A5 JP2024519492 A5 JP 2024519492A5
Authority
JP
Japan
Prior art keywords
layer
photoresist
pattern
relief pattern
wavelength
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023567953A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024519492A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2022/026697 external-priority patent/WO2022235475A1/en
Publication of JP2024519492A publication Critical patent/JP2024519492A/ja
Publication of JP2024519492A5 publication Critical patent/JP2024519492A5/ja
Pending legal-status Critical Current

Links

JP2023567953A 2021-05-03 2022-04-28 ウェット-ドライ二層レジスト Pending JP2024519492A (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US202163183130P 2021-05-03 2021-05-03
US202163183129P 2021-05-03 2021-05-03
US202163183128P 2021-05-03 2021-05-03
US63/183,130 2021-05-03
US63/183,128 2021-05-03
US63/183,129 2021-05-03
PCT/US2022/026697 WO2022235475A1 (en) 2021-05-03 2022-04-28 Wet-dry bilayer resist

Publications (2)

Publication Number Publication Date
JP2024519492A JP2024519492A (ja) 2024-05-14
JP2024519492A5 true JP2024519492A5 (enExample) 2025-04-17

Family

ID=83807790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023567953A Pending JP2024519492A (ja) 2021-05-03 2022-04-28 ウェット-ドライ二層レジスト

Country Status (5)

Country Link
US (3) US12327726B2 (enExample)
JP (1) JP2024519492A (enExample)
KR (1) KR102972540B1 (enExample)
TW (1) TW202307957A (enExample)
WO (1) WO2022235475A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024519492A (ja) * 2021-05-03 2024-05-14 東京エレクトロン株式会社 ウェット-ドライ二層レジスト
US12538760B2 (en) * 2021-11-22 2026-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device
US20250149335A1 (en) * 2023-11-07 2025-05-08 Tokyo Electron Limited Method to pattern a semiconductor substrate using a multilayer photoresist film stack

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5626450A (en) * 1979-08-13 1981-03-14 Hitachi Ltd Manufacture of semiconductor device
JPH01128522A (ja) * 1987-11-13 1989-05-22 Fujitsu Ltd レジストパターンの形成方法
JP2794118B2 (ja) * 1989-05-16 1998-09-03 三菱電機株式会社 微細パターンの形成方法
JPH0566568A (ja) * 1991-09-06 1993-03-19 Kawasaki Steel Corp 多重コントラストレジストパターンの製造方法、及び多層レジスト
JPH0737789A (ja) * 1993-07-22 1995-02-07 Toray Ind Inc 二層構造レジストを有する基材の製造方法
US6410453B1 (en) * 1999-09-02 2002-06-25 Micron Technology, Inc. Method of processing a substrate
TW439118B (en) * 2000-02-10 2001-06-07 Winbond Electronics Corp Multilayer thin photoresist process
JP2003043697A (ja) * 2001-07-31 2003-02-13 Ricoh Co Ltd 多層レジストパターン形成方法
US7229745B2 (en) * 2004-06-14 2007-06-12 Bae Systems Information And Electronic Systems Integration Inc. Lithographic semiconductor manufacturing using a multi-layered process
KR100584681B1 (ko) * 2004-06-30 2006-05-30 재단법인서울대학교산학협력재단 다층감광막을 이용한 패턴의 선택적 형성 방법
KR20060054666A (ko) * 2004-11-15 2006-05-23 삼성전자주식회사 다층의 포토레지스트 패턴 구조를 갖는 반도체소자 및 그제조방법
US7579137B2 (en) * 2005-12-24 2009-08-25 International Business Machines Corporation Method for fabricating dual damascene structures
US20080199814A1 (en) * 2006-12-06 2008-08-21 Fujifilm Electronic Materials, U.S.A., Inc. Device manufacturing process utilizing a double patterning process
US8110339B2 (en) * 2007-09-06 2012-02-07 Massachusetts Institute Of Technology Multi-tone resist compositions
JP2010040849A (ja) * 2008-08-06 2010-02-18 Tokyo Ohka Kogyo Co Ltd レジストパターン形成方法
JP4671065B2 (ja) * 2008-09-05 2011-04-13 信越化学工業株式会社 ダブルパターン形成方法
US8435723B2 (en) * 2008-09-11 2013-05-07 Nikon Corporation Pattern forming method and device production method
US8283111B2 (en) * 2008-09-17 2012-10-09 Tokyo Electron Limited Method for creating gray-scale features for dual tone development processes
US8197996B2 (en) 2008-09-19 2012-06-12 Tokyo Electron Limited Dual tone development processes
US8129080B2 (en) 2008-09-19 2012-03-06 Tokyo Electron Limited Variable resist protecting groups
US8492282B2 (en) * 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
JP5337180B2 (ja) * 2010-04-08 2013-11-06 東京エレクトロン株式会社 塗布処理方法、プログラム、コンピュータ記憶媒体及び塗布処理装置
US9274426B2 (en) * 2014-04-29 2016-03-01 Az Electronic Materials (Luxembourg) S.A.R.L. Antireflective coating compositions and processes thereof
JP6378146B2 (ja) * 2014-10-16 2018-08-22 信越化学工業株式会社 多層膜形成方法及びパターン形成方法
TWI632437B (zh) * 2014-11-07 2018-08-11 羅門哈斯電子材料有限公司 用於形成凸紋影像的方法
JP6580142B2 (ja) * 2014-12-22 2019-09-25 ユーリタ アクチエンゲゼルシャフトEulitha Ag カラー画像を印刷する方法
US9996004B2 (en) * 2015-11-20 2018-06-12 Lam Research Corporation EUV photopatterning of vapor-deposited metal oxide-containing hardmasks
US10366890B2 (en) * 2016-05-23 2019-07-30 Tokyo Electron Limited Method for patterning a substrate using a layer with multiple materials
US11764062B2 (en) * 2017-11-13 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
US10636667B2 (en) * 2017-11-21 2020-04-28 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor devices and structures thereof
US20200411317A1 (en) * 2019-06-26 2020-12-31 Intel Corporation Integrated circuit package assemblies with high-aspect ratio metallization features
CN114585969B (zh) * 2019-09-19 2025-02-07 东京毅力科创株式会社 形成窄沟槽的方法
JP2024519492A (ja) * 2021-05-03 2024-05-14 東京エレクトロン株式会社 ウェット-ドライ二層レジスト

Similar Documents

Publication Publication Date Title
US8907456B2 (en) Multi-material hard mask or prepatterned layer for use with multi-patterning photolithography
JP7554539B2 (ja) 狭小トレンチを形成する方法
JP5079012B2 (ja) パターン化された材料層を形成する方法
CN107112212A (zh) 使用接枝聚合物材料图案化基底
US11393694B2 (en) Method for planarization of organic films
CN107851557A (zh) 形成用于基板图案化的掩模的方法
JP2009534870A (ja) パターン内の最小ピッチを短縮させる方法
US5902493A (en) Method for forming micro patterns of semiconductor devices
TW202307957A (zh) 乾溼雙層光阻
US7914975B2 (en) Multiple exposure lithography method incorporating intermediate layer patterning
US12455507B2 (en) Method for removing material overburden via enhanced freeze-less anti-spacer formation using a bilayer system
KR101096270B1 (ko) 스페이서 패터닝을 이용한 반도체소자의 미세패턴 형성방법
JPS63170917A (ja) 微細パタ−ンの形成方法
KR20250113430A (ko) 반도체 형상부 패터닝
CN117461111A (zh) 干湿双层抗蚀剂
KR20240011641A (ko) 마스크 형성을 위한 이차 레지스트 표면 기능화를 이용하는패터닝 방법
US20090092933A1 (en) Methods of Lithographically Patterning a Substrate
JPH0566568A (ja) 多重コントラストレジストパターンの製造方法、及び多層レジスト
KR100928513B1 (ko) 반도체 소자의 제조방법
JPS58153932A (ja) 写真蝕刻方法
JPH1172913A (ja) ネガ型レジストおよびレジストパターン形成方法
JPS6236823A (ja) レジストパタ−ン形成方法
JPH035654B2 (enExample)
JPH0253061A (ja) 2層レジスト構造
JPS6286824A (ja) 高解像度レジストパタ−ンニング方法