JP2023549685A5 - - Google Patents

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Publication number
JP2023549685A5
JP2023549685A5 JP2023526096A JP2023526096A JP2023549685A5 JP 2023549685 A5 JP2023549685 A5 JP 2023549685A5 JP 2023526096 A JP2023526096 A JP 2023526096A JP 2023526096 A JP2023526096 A JP 2023526096A JP 2023549685 A5 JP2023549685 A5 JP 2023549685A5
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JP
Japan
Prior art keywords
integrated device
substrate
interconnect
interconnection
cavity
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JP2023526096A
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English (en)
Japanese (ja)
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JP7823041B2 (ja
JP2023549685A (ja
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Priority claimed from US17/094,303 external-priority patent/US12355000B2/en
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Publication of JP2023549685A publication Critical patent/JP2023549685A/ja
Publication of JP2023549685A5 publication Critical patent/JP2023549685A5/ja
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Publication of JP7823041B2 publication Critical patent/JP7823041B2/ja
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JP2023526096A 2020-11-10 2021-10-07 基板と高密度相互接続集積デバイスとを含むパッケージ Active JP7823041B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/094,303 US12355000B2 (en) 2020-11-10 2020-11-10 Package comprising a substrate and a high-density interconnect integrated device
US17/094,303 2020-11-10
PCT/US2021/054044 WO2022103531A1 (en) 2020-11-10 2021-10-07 Package comprising a substrate and a high-density interconnect integrated device

Publications (3)

Publication Number Publication Date
JP2023549685A JP2023549685A (ja) 2023-11-29
JP2023549685A5 true JP2023549685A5 (https=) 2024-10-01
JP7823041B2 JP7823041B2 (ja) 2026-03-03

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Family Applications (1)

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JP2023526096A Active JP7823041B2 (ja) 2020-11-10 2021-10-07 基板と高密度相互接続集積デバイスとを含むパッケージ

Country Status (7)

Country Link
US (1) US12355000B2 (https=)
EP (1) EP4244891A1 (https=)
JP (1) JP7823041B2 (https=)
KR (1) KR20230098583A (https=)
CN (1) CN116508154A (https=)
TW (1) TWI905286B (https=)
WO (1) WO2022103531A1 (https=)

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