JP2023522847A5 - - Google Patents

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Publication number
JP2023522847A5
JP2023522847A5 JP2022560881A JP2022560881A JP2023522847A5 JP 2023522847 A5 JP2023522847 A5 JP 2023522847A5 JP 2022560881 A JP2022560881 A JP 2022560881A JP 2022560881 A JP2022560881 A JP 2022560881A JP 2023522847 A5 JP2023522847 A5 JP 2023522847A5
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Japan
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target
layer
dlst
minimum dimension
typical minimum
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JP2022560881A
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Japanese (ja)
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JP2023522847A (ja
JP7369306B2 (ja
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Priority claimed from PCT/US2020/039475 external-priority patent/WO2021211154A1/en
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JP2022560881A 2020-04-15 2020-06-25 半導体デバイスの位置ずれを計測する際役立つデバイス規模フィーチャを有する位置ずれターゲット Active JP7369306B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202063010096P 2020-04-15 2020-04-15
US63/010,096 2020-04-15
PCT/US2020/039475 WO2021211154A1 (en) 2020-04-15 2020-06-25 Misregistration target having device-scaled features useful in measuring misregistration of semiconductor devices

Publications (3)

Publication Number Publication Date
JP2023522847A JP2023522847A (ja) 2023-06-01
JP2023522847A5 true JP2023522847A5 (https=) 2023-06-20
JP7369306B2 JP7369306B2 (ja) 2023-10-25

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JP2022560881A Active JP7369306B2 (ja) 2020-04-15 2020-06-25 半導体デバイスの位置ずれを計測する際役立つデバイス規模フィーチャを有する位置ずれターゲット

Country Status (7)

Country Link
US (1) US11532566B2 (https=)
EP (1) EP4111495A4 (https=)
JP (1) JP7369306B2 (https=)
KR (1) KR102630496B1 (https=)
CN (1) CN115428139B (https=)
TW (1) TWI851889B (https=)
WO (1) WO2021211154A1 (https=)

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US12014961B2 (en) * 2021-04-19 2024-06-18 Nanya Technology Corporation Method of semiconductor overlay measuring and method of semiconductor structure manufacturing
US11703767B2 (en) * 2021-06-28 2023-07-18 Kla Corporation Overlay mark design for electron beam overlay
US12094100B2 (en) * 2022-03-03 2024-09-17 Kla Corporation Measurement of stitching error using split targets
US12354970B2 (en) 2022-04-08 2025-07-08 Nanya Technology Corporation Semiconductor device structure with overlay mark
TWI809929B (zh) * 2022-04-08 2023-07-21 南亞科技股份有限公司 具有疊對標記的半導體元件結構
US12243832B2 (en) 2022-04-08 2025-03-04 Nanya Technology Corporation Method for manufacturing semiconductor device structure with overlay marks
US12416867B2 (en) * 2022-09-22 2025-09-16 United Microelectronics Corp. Overlay target and overlay method

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US8804137B2 (en) * 2009-08-31 2014-08-12 Kla-Tencor Corporation Unique mark and method to determine critical dimension uniformity and registration of reticles combined with wafer overlay capability
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US10551749B2 (en) * 2017-01-04 2020-02-04 Kla-Tencor Corporation Metrology targets with supplementary structures in an intermediate layer
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KR102778014B1 (ko) * 2017-11-29 2025-03-06 케이엘에이 코포레이션 디바이스 검사 시스템을 사용한 오버레이 에러의 측정
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US10446367B2 (en) * 2018-03-07 2019-10-15 Kla-Tencor Corporation Scan strategies to minimize charging effects and radiation damage of charged particle beam metrology system
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