JP2022529077A5 - - Google Patents

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Publication number
JP2022529077A5
JP2022529077A5 JP2021573602A JP2021573602A JP2022529077A5 JP 2022529077 A5 JP2022529077 A5 JP 2022529077A5 JP 2021573602 A JP2021573602 A JP 2021573602A JP 2021573602 A JP2021573602 A JP 2021573602A JP 2022529077 A5 JP2022529077 A5 JP 2022529077A5
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Japan
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layer
periodic structure
misalignment
measuring
image
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JP2021573602A
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Japanese (ja)
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JP2022529077A (ja
JP7254217B2 (ja
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Priority claimed from PCT/US2020/018202 external-priority patent/WO2020168142A1/en
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Publication of JP2022529077A5 publication Critical patent/JP2022529077A5/ja
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JP2021573602A 2019-02-14 2020-02-14 誘導されたトポグラフィを利用した半導体デバイスウェハの位置ずれを測定するためのシステムと方法 Active JP7254217B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201962805737P 2019-02-14 2019-02-14
US62/805,737 2019-02-14
US201962864323P 2019-06-20 2019-06-20
US62/864,323 2019-06-20
US201962870264P 2019-07-03 2019-07-03
US62/870,264 2019-07-03
PCT/US2020/018202 WO2020168142A1 (en) 2019-02-14 2020-02-14 System and method for measuring misregistration of semiconductor device wafers utilizing induced topography

Publications (3)

Publication Number Publication Date
JP2022529077A JP2022529077A (ja) 2022-06-16
JP2022529077A5 true JP2022529077A5 (https=) 2023-02-20
JP7254217B2 JP7254217B2 (ja) 2023-04-07

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JP2021573602A Active JP7254217B2 (ja) 2019-02-14 2020-02-14 誘導されたトポグラフィを利用した半導体デバイスウェハの位置ずれを測定するためのシステムと方法
JP2021574301A Active JP7595599B2 (ja) 2019-02-14 2020-02-14 トポグラフィ半導体デバイスウェハの製造における位置ずれの測定方法

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JP2021574301A Active JP7595599B2 (ja) 2019-02-14 2020-02-14 トポグラフィ半導体デバイスウェハの製造における位置ずれの測定方法

Country Status (5)

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US (3) US11281112B2 (https=)
EP (2) EP3970184A4 (https=)
JP (2) JP7254217B2 (https=)
TW (2) TWI814987B (https=)
WO (2) WO2020168142A1 (https=)

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