JP2022143051A5 - - Google Patents

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JP2022143051A5
JP2022143051A5 JP2021043381A JP2021043381A JP2022143051A5 JP 2022143051 A5 JP2022143051 A5 JP 2022143051A5 JP 2021043381 A JP2021043381 A JP 2021043381A JP 2021043381 A JP2021043381 A JP 2021043381A JP 2022143051 A5 JP2022143051 A5 JP 2022143051A5
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JP2021043381A
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JP7413303B2 (ja
JP2022143051A (ja
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Priority to JP2021043381A priority Critical patent/JP7413303B2/ja
Priority claimed from JP2021043381A external-priority patent/JP7413303B2/ja
Priority to CN202110906326.0A priority patent/CN115117051B/zh
Priority to US17/469,819 priority patent/US12142604B2/en
Publication of JP2022143051A publication Critical patent/JP2022143051A/ja
Publication of JP2022143051A5 publication Critical patent/JP2022143051A5/ja
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JP2021043381A 2021-03-17 2021-03-17 半導体装置及び半導体システム Active JP7413303B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2021043381A JP7413303B2 (ja) 2021-03-17 2021-03-17 半導体装置及び半導体システム
CN202110906326.0A CN115117051B (zh) 2021-03-17 2021-08-09 半导体装置以及半导体系统
US17/469,819 US12142604B2 (en) 2021-03-17 2021-09-08 Semiconductor device and semiconductor system including electro static discharge (ESD) protective device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2021043381A JP7413303B2 (ja) 2021-03-17 2021-03-17 半導体装置及び半導体システム

Publications (3)

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JP2022143051A JP2022143051A (ja) 2022-10-03
JP2022143051A5 true JP2022143051A5 (enExample) 2023-02-06
JP7413303B2 JP7413303B2 (ja) 2024-01-15

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JP2021043381A Active JP7413303B2 (ja) 2021-03-17 2021-03-17 半導体装置及び半導体システム

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US (1) US12142604B2 (enExample)
JP (1) JP7413303B2 (enExample)
CN (1) CN115117051B (enExample)

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4035820A (en) * 1975-12-29 1977-07-12 Texas Instruments Incorporated Adjustment of avalanche voltage in DIFMOS memory devices by control of impurity doping
US4989057A (en) 1988-05-26 1991-01-29 Texas Instruments Incorporated ESD protection for SOI circuits
JPH0837284A (ja) 1994-07-21 1996-02-06 Nippondenso Co Ltd 半導体集積回路装置
JPH08195443A (ja) * 1995-01-18 1996-07-30 Fujitsu Ltd 半導体装置及びその製造方法
US6521952B1 (en) * 2001-10-22 2003-02-18 United Microelectronics Corp. Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection
JP4102277B2 (ja) 2003-09-12 2008-06-18 株式会社東芝 半導体集積回路装置
US7570468B2 (en) * 2006-07-05 2009-08-04 Atmel Corporation Noise immune RC trigger for ESD protection
DE102008001368A1 (de) 2008-04-24 2009-10-29 Robert Bosch Gmbh Flächenoptimierte ESD-Schutzschaltung
JP5273604B2 (ja) 2008-08-22 2013-08-28 株式会社メガチップス Ｅｓｄ保護回路
CN102315212B (zh) * 2010-06-29 2015-10-21 上海华虹宏力半导体制造有限公司 栅驱动晶闸管电路以及静电保护电路
US8861149B2 (en) * 2011-01-07 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. ESD protection devices and methods for forming ESD protection devices
JP2012253241A (ja) * 2011-06-03 2012-12-20 Sony Corp 半導体集積回路およびその製造方法
JP2014026996A (ja) 2012-07-24 2014-02-06 Toshiba Corp Ｅｓｄ保護回路
CN103646945B (zh) * 2013-12-03 2017-02-15 北京中电华大电子设计有限责任公司 集成电路电源esd保护电路
JP6623139B2 (ja) 2016-10-24 2019-12-18 株式会社東芝 Ｅｓｄ保護回路
JP7071359B2 (ja) 2017-07-12 2022-05-18 ソニーセミコンダクタソリューションズ株式会社 トランジスタ及び電子機器

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