JPH02210860A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPH02210860A
JPH02210860A JP1032160A JP3216089A JPH02210860A JP H02210860 A JPH02210860 A JP H02210860A JP 1032160 A JP1032160 A JP 1032160A JP 3216089 A JP3216089 A JP 3216089A JP H02210860 A JPH02210860 A JP H02210860A
Authority
JP
Japan
Prior art keywords
type
layer
voltage
substrate
conductivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1032160A
Other languages
English (en)
Inventor
Koichi Suzuki
康一 鈴木
Norihito Miyoshi
則仁 三好
Makoto Yoshida
誠 吉田
Masayuki Komon
小門　正之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1032160A priority Critical patent/JPH02210860A/ja
Priority to EP19900301286 priority patent/EP0382504A3/en
Priority to KR1019900001560A priority patent/KR930001220B1/ko
Priority to US07/477,544 priority patent/US5065216A/en
Publication of JPH02210860A publication Critical patent/JPH02210860A/ja
Priority to US07/757,640 priority patent/US5240867A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔概　要〕 チップ背面より電源を供給する半導体集積回路装置に関
し、 チップ背面から供給する電源電圧の選択範囲を広くする
ことを目的とし、 裏面に電極層を設けた第１導電型基板の上に高抵抗の第
２導電型層と素子形成用の第１導電型層を順に積層した
状態で、上記第１導電型層に第２導電型アイソレージジ
ンを設けるとともに、上記第１導電型層及び上記第２導
電型層の一部の所載に、第１導電型基板に達する第１Ｒ
電型の電源供給用高導電層を形成したことを含み構成す
る。
〔産業上の利用分野〕
本発明は、半導体集積回路装置に関し、より詳しくは、
チップ背面より電源を供給する半導体集積回路装置に関
する。
〔従来の技術〕
半導体集積回路装置においては、高速化や高集積化が進
むにつれて、装置内の信号配線の数が増加するとともに
集積回路の消費電力が増加している。
また、バイポーラトランジスタを備えた装置では、高速
動作を図るために大きな電流を流す必要があり、配線層
の幅が大きくなってきている。
このため、信号線、電源線の配線の自由度が低下したり
、配線に要する面積の増大に伴って半導体装置の小型化
が図れなくなるといった問題が発生する。
この問題を解決するために本出願人は、第４図（ａ）に
示すように、ｐ°型基板４０の上に高抵抗のρ−型エピ
タキシャル層４１、素子形成用のｎ型エピタキシャル層
４２を順に積層するとともに、ｎ型エピタキシャル層４
２及びｐ−型エピタキシャル層４１の各々に低抵抗の２
０型アイソレーシヨンＪｉ１４３及びｐ゛型Ｊｌｉ１４
４を連続的に形成することによりｐ０型基板４０の底面
に形成したメタライズＮ４５に印加する電圧ｖ！ｔを、
ｐ１型アイソレーシゴンｊ１４３及びｐ９型Ｎ４４を介
して表面側のトランジスタ等に安定供給するようにした
装置を特願昭６２−２３０２５８号において提案した。
この装置によれば、電圧ｖ０を基板４１表側に供給する
ために必要な電極配線の面積を小さくするとともに、そ
の配線を分散させて信号配線の自由度を向上できること
になる。
〔発明が解決しようとする課題〕
しかし、この装置においては、ｐ９型アイソレーション
層４３とｎ型エピタキシャル層４２との接合部分に寄生
ダイオードが発生するため、この寄生ダイオードに正バ
イアス電圧を印加しないようにする必要があり、メタラ
イズ１４５に印加できる電圧は最も小さい電位に限定さ
れることになり、裏面のメタライズ層４５からそれより
も高い電圧を印加できないといった問題がある。
また、このような問題は基板をｎ型とした場合にも発生
する。すなわち、第４図（ｂ）に示すように、ｎ０型基
板４６の上にｎ−型層４７と素子形成用Ｐ型層４８を順
に形成するとともに、ｐ型層４８からｎ′″型基１ｉ４
６の上部に達するｎ°型アイソレージ四ン層４７及びｎ
０型層４９を連続的に形成する場合には、裏面のメタラ
イズ層５０に印加する電圧は最も高い電圧に限られるこ
とになり、それよりも低い電圧を印加できないことにな
る。
本発明は、このような問題に鑑みてなされたものであっ
て、チップ背面から供給する電源電圧の選択範囲を広く
することができる半導体集積回路装置を提供することを
目的とする。
〔課題を解決するための手段〕
上記した課題は、第１図の原理図において、裏面に電極
層３０を設けた第１導電型基ｖｉ３１の上に高抵抗の第
２導電型層３２と素子形成用の第１導電型１１３３を順
に積層した状態で、上記第１導電型７１３３に第２導電
型アイソレーション３４を設けるとともに、上記第１１
電型Ｍ３３及び上記第２導電型層３２の一部の領域に、
上記第１導電型基板３１に達する第ｔｉ電型の電源供給
用高導電１１３５を形成したことを特徴とする半導体集
積回路装置により解決する。
（作　用〕 本発明において、まず、第１導電型をｎ型、第２導電型
をｐ型とした場合について説明する。
この場合には、素子形成用ｎ型！！３３に形成したＰ型
アイソレーション３４に最も低い電圧を印加することに
なるので、高抵抗のｐ型層３２、素子形成用のｎ型Ｎ３
３とｎ型の電源供給用高導電ＪＩ１３５との間に正バイ
アスの電圧が加わることがない。
したがって、ｎ型基板３１の裏面に形成した電極１３０
に印加する電圧は最も低い電圧に限られず、電極層３０
に印加する電圧を、電源供給用の高導電１３５を通して
ｎ型基板３１の表側に供給することができる。
次に、第１導電型をｐ型、第２導電型をｎ型とした場合
について説明する。
この場合には、素子形成用のｐ型層３３に形成するｎ型
アイソレージタン３４に最も高い電圧を印加することに
なるので、高抵抗のｎ型層３２、素子形成用のｐ型層３
３とｐ型の電源供給用高電導層３５との間に正バイアス
の電圧が加わることがない。
したがって、ｎ型基［３１の裏面に形成する電極層３０
に印加する電圧は最も高い電圧に限定されず、電極層３
０に印加する電圧を電源供給用高導電層３５を通してＰ
型基板３１の表側に供給できることになる。
さらに、本発明では、第１導電型基板３１と素子形成用
の第１導電型層３３との間に第２導電型層３２を挟むよ
うにしたので、電極３０に電圧を印加する場合に、いず
れかの接合面が逆バイアスとなるために、電極層３０の
電圧が第１導電型層３３に加わることはない。
［実施例〕 （ａ）発明の一実施例の説明 第２図は、本発明の一実施例を示す装置の断面図であっ
て、図中符号！は、不純物濃度を高くすることにより抵
抗率を０．１０１以下としたｎ°型半導体基板で、その
裏面には金等の導電材よりなる電極Ｎ２が形成され、ま
た表面には、１〜３０Ω１程度の高抵抗のｐ−型半導体
層３と素子形成用のれ一型半導体層４が順にエピタキシ
ャル成長されている。
５は、ｎ−型半導体層４からｎ°型半導体基板１の上部
に達する溝６の中に埋め込まれたｎ０ドープトポリシリ
コンよりなる高導電層で、この高導電層５は、溝６の内
周壁に形成された絶縁１ｆ１７によってｎ−型半導体層
４及びｐ−型半導体層３から絶縁される一方、その底面
を低抵抗のｎ３型半導体基板１に接合させることにより
、裏面の電極層２に印加した電圧Ｖを表側に導くように
構成されている。
８は、ｎ−型半導体Ｎ４に形成したバイポーラトランジ
スタで、このトランジスタ８は、ｎ−型半導体層４の下
層部をコレクタＣとして用いるとともに、上層部にｐ型
不純物、ｎｆｉ型不純物を順に拡散してこれらをベース
ｂ及びエミッタｅとして適用したもので、エミッタｅ又
はコレクタＣの上の電極９、ｌＯと高導電層５とを基板
１表面側のアルミニウム配線層１８を芥して導通するこ
とにより、電極Ｎ２に加えた電圧Ｖがエミッタｅ又はコ
レクタＣに印加し得るように構成されている。
１４は、ｎ−型半導体層４中に設けたｐ゛型テアイソレ
ージジン、ｎ−型半導体層４にｐ型元素を拡散して形成
されており、その深さはｐ−型半導体層３に達するよう
に構成されている。
なお、図中符号ＩＩは、トランジスタ８を形成する領域
のｎ−型半導体Ｎ４とＰ−型半導体層３との間に形成し
た埋込層、１２は、コレクタＣ及び埋込層１１に接合さ
れるコレクタＣ用の補償拡散層、１３は、Ｐ９型アイソ
レーシッン１４に最も低い電圧を供給するための電極、
１５は、素子分離用の絶ｓｉｎ、１６はベース用の電極
、１７は基板！保護用の絶縁膜、！９は、基板１！面の
電極Ｎ２を導電状態で載置する導電性リードフレームの
ステージを示している。
次に、上述した実施例の作用について説明する。
まず、トランジスタ８のコレクタＣと高電導層５とをア
ルミニウム配線層１８により導通する場合について述べ
る。
上記した実施例において、リードフレームのステージ１
９を通して電極層２に最も高い電圧ＶＣＣを印加すると
、ｎ゛゛半導体基板１を介して電極層２と導通している
高電導Ｎ５はＶＣＣの電圧となる。
この状態では、ｎ゛゛半導体基板１とその上のｐ−型半
導体層３との接合部分が逆バイアスとなっているために
、ｐ−型半導体層３からｎ−型半導体Ｎ４に電圧ｖｃｃ
が加わることはない。
また、ｎ４型半導体基板１表側のトランジスタ８のコレ
クタＣには、ｎ３型の高電導層５に印加した電圧■。が
アルミニウム配線層１８を介して加わることになる。
次に、高電導層５とエミッタｅとをアルミニウム配線Ｎ
１８により導通する場合について説明する。
この場合において、電極層２に最も低い電圧ｖ０を印加
すると、ｎ°型半導体基板１、高電導Ｎ５及びアルミニ
ウム配線層１８を介してエミッタＣはＶｔｔの電位とな
る。
また、ｎ゛型半導体基板ｌとその上のｐ−型半導体層３
との接合部分に生じる寄生ダイオードには正方向の電圧
が印加する事になるが、ｐ−型半導体層３とその上のｎ
−型半導体Ｎ４との接合部分においては逆バイアスとな
るため、ｎ−型半導体Ｎ４の電圧がＶｌｔとなることは
ない。
（ｂ）本発明のその他の実施例の説明 上記した実施例では、ｎｏ　ドープトポリシリコンによ
り高電導層５を形成したが、第３図（ａ）に示すように
、ｎ゛゛元素をＰ−型半導体Ｎ３及びｎ−型半導体層４
に拡散し、これを高電導Ｍ２０とすることもできる。
この状態において、電極層２に最も高い電圧ｖｃｃを印
加すると、ｐ−型半導体７１３にはＰ０アイソレーショ
ン１４を介して最も低い電圧が印加されているため、ｐ
−型半導体Ｍ３と高電導層２０との間に逆バイアスの電
圧が印加することになってｐ−型半導体Ｎ３にＶＣＣの
電圧が印加することはない。
また、電極層２に最も低い電圧Ｖ０を印加する場合には
、Ｐ−型半導体層３と高電導Ｎ２０は同一の電圧となり
、ｐ−型半導体層３の特性を変えることはない。
さらに、トランジスタ８を形成する領域のｎ−型半導体
層４は、ｐ“型アイソレーション１４によって高電導Ｊ
１２０と絶縁されているので、電圧ＶＣＣ１ＶｔＥがト
ランジスタ８に印加することはない。
また、上記した第１の実施例では、高電導層５をｎ１ド
ープトポリシリコンより形成したが、ｎｏ　ドープトポ
リシリコンの上に金属シリサイド膜を重ねたポリサイド
によって高電導層５を構成することもできる。
さらに、上記した実施例の２０型アイソレーシヨン１４
はＰ型元素をｎ−型半導体層４に拡散して形成したもの
であるが、第３図（ｂ）に示すように、ｎ−型半導体Ｎ
４に溝２１を形成し、この溝２１の内周壁に絶縁膜２２
を形成した状態でこの満２１の中にＰ゛型トープトポ’
ＩＪシリコンを埋め込んで、これをｐ′″型アイソレー
シッン２４とすることもできる。
なお、上記した実施例では、ｎ゛型の半導体基板１を使
用したがｐ′型のものを使用することもできる。この場
合に、半導体基板の上にエピタキシャル成長させる層は
、ｎ−型半導体層、ｐ゛型型溝導体層順になり、ｐ００
型半導層に形成するアイソレーションはｎ０型となって
ここに最も高い電圧を印加することになる。
〔発明の効果〕
以上述べたように本発明によれば、素子形成用半導体層
の導電型と同一の導電型の半導体基板を使用し、これら
の間に反対ｓＩｉ型の半導体層を形成するとともに、半
導体基板の裏面から表側に電源を供給する高導電層を素
子形成層と同一の導電型としたので、苦手導体層の接合
部分に逆バイアスが加わることがなく、半導体基板の裏
面に印加する電圧の範囲を広げることができる。
【図面の簡単な説明】
第１図は、本発明の原理図、 第２図は、本発明の一実施例を示す装置の断面図、 第３図（ａ）　、　（ｂ）は、本発明のその他の実施例
を示す装置の部分断面図、 第４図（ａ）　、　（ｂ）は、従来装置の一例を示す断
面図である。 （符号の説明） １・・・ｎ９型半導体基板、 ２・・・電極層、 ３・・・ｐ〜型型厚導体層 ４・・・ｎ−型半導体層、 ５．２０・・・高電Ｒ＊、 ８・・・トランジスタ、 １４．２４・・・ｐ９型アイソレーション、１８・・・
アルミニウム配線層、 ３０・・・電極層、 ３１・・・第１導電型基板、 ３２・・・第２導電型層、 ３３・・・第１導電型層、 ３４・・・第２導電型アイソレーション、３５・・・高
導電層。

Claims (1)

  1. 【特許請求の範囲】 裏面に電極層（３０）を設けた第１導電型基板（３１）
    の上に高抵抗の第２導電型層（３２）と素子形成用の第
    １導電型層（３３）を順に積層した状態で、 上記第１導電型層（３３）に第２導電型アイソレーショ
    ン（３４）を設けるとともに、 上記第１導電型層（３３）及び上記第２導電型層（３２
    ）の一部の領域に、上記第１導電型基板（３１）に達す
    る第１導電型の電源供給用高導電層（３５）を形成した
    ことを特徴とする半導体集積回路装置。
JP1032160A 1989-02-09 1989-02-09 半導体集積回路装置 Pending JPH02210860A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP1032160A JPH02210860A (ja) 1989-02-09 1989-02-09 半導体集積回路装置
EP19900301286 EP0382504A3 (en) 1989-02-09 1990-02-07 Semiconductor integrated circuit having interconnection with improved design flexibility
KR1019900001560A KR930001220B1 (ko) 1989-02-09 1990-02-09 반도체 집적회로 장치 및 그의 제조방법
US07/477,544 US5065216A (en) 1989-02-09 1990-02-09 Semiconductor integrated circuit having interconnection with improved design flexibility, and method of production
US07/757,640 US5240867A (en) 1989-02-09 1991-09-11 Semiconductor integrated circuit having interconnection with improved design flexibility, and method of production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1032160A JPH02210860A (ja) 1989-02-09 1989-02-09 半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPH02210860A true JPH02210860A (ja) 1990-08-22

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Country Link
US (1) US5065216A (ja)
EP (1) EP0382504A3 (ja)
JP (1) JPH02210860A (ja)
KR (1) KR930001220B1 (ja)

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EP0382504A3 (en) 1992-08-26
US5065216A (en) 1991-11-12
EP0382504A2 (en) 1990-08-16
KR900013634A (ko) 1990-09-06
KR930001220B1 (ko) 1993-02-22

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