JP2022140554A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2022140554A JP2022140554A JP2022117079A JP2022117079A JP2022140554A JP 2022140554 A JP2022140554 A JP 2022140554A JP 2022117079 A JP2022117079 A JP 2022117079A JP 2022117079 A JP2022117079 A JP 2022117079A JP 2022140554 A JP2022140554 A JP 2022140554A
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- insulator
- oxide
- conductor
- transistor
- wiring
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Abstract
Description
本実施の形態では、本発明の一態様に係る半導体装置の構成例について説明する。
図1に、本発明の一態様に係る半導体装置10の構成例を示す。半導体装置10は、記憶装置としての機能を有する。そのため、半導体装置10は記憶装置と呼ぶこともできる。
次に、センスアンプSAの構成例及び動作例について説明する。ここでは一例として、メモリセルMCと接続されたセンスアンプSA、すなわち、センスアンプアレイSAAに用いられるセンスアンプSAについて説明する。ただし、以下に説明するセンスアンプSAは、グローバルセンスアンプGSAに用いることもできる。
図8に、センスアンプSAの回路構成の一例を示す。ここでは、配線WLa及び配線BLaと接続されたメモリセルMCa、配線WLb及び配線BLbと接続されたメモリセルMCb、メモリセルMCa、MCbと接続されたセンスアンプSAを例示している。メモリセルMCa、MCbには、図2(B-1)に示す構成を用いている。センスアンプSAは、増幅回路AC、スイッチ回路SC、プリチャージ回路PRCを有する。
次に、メモリセルMCaからデータを読み出す際のセンスアンプSAの動作の一例について、図9に示したタイミングチャートを用いて説明する。
本実施の形態では、上記実施の形態で説明した半導体装置を用いたコンピュータの構成例について説明する。
次いで、本発明の一態様に係る半導体装置の、メモリセルが有するトランジスタ及び容量素子の構成について説明する。
トランジスタを形成する基板としては、例えば、絶縁体基板、半導体基板または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えばSOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体405_1、導電体405_2、導電体460a、導電体460b、導電体440、導電体510a、導電体510b、導電体520a及び導電体520bとしては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を1種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
以下では、本発明の一態様で開示されるトランジスタに用いることができるCAC(Cloud-Aligned Composite)-OSの構成について説明する。
酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC-OS(C-Axis Aligned Crystalline Oxide Semiconductor)、多結晶酸化物半導体、nc-OS(nanocrystalline Oxide Semiconductor)、擬似非晶質酸化物半導体(a-like OS:amorphous-like Oxide Semiconductor)及び非晶質酸化物半導体などがある。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
2つのメモリセルが一のビット線を共有する場合における、トランジスタ400a、トランジスタ400b、容量素子500a及び容量素子500bの別の構成例を、図13に示す。図13に示す断面図では、トランジスタ400aと容量素子500aとは第1のメモリセルに含まれており、トランジスタ400bと容量素子500bとは第2のメモリセルに含まれている。
同様に、酸化物430のうち、導電体442cと重なる領域、より具体的には導電体442cと接する酸化物430の表面近傍の領域443cには、チャネル形成領域よりも抵抗の低い低抵抗領域が形成される場合がある。上記領域を有することにより、酸化物430と導電体442a、導電体442b、または導電体442cとの間の接触抵抗を低減させることができ、トランジスタ400a及びトランジスタ400bのオン電流を高めることができる。
次に、図11に示したトランジスタ400a、トランジスタ400b、容量素子500a及び容量素子500bを有する半導体装置の作製方法について、図14乃至図27を用いて説明する。図14乃至図27において、各図の(A)は、上面図である。各図の(B)は各図の(A)の一点鎖線A1-A2における断面図である。また、各図の(C)は、各図の(A)の一点鎖線A3-A4における断面図である。
本実施の形態では、半導体装置の一形態を、図12を用いて説明する。図12に示す半導体装置は、トランジスタ600の上方に、図11に示したトランジスタ400a、容量素子500a、トランジスタ400b、及び容量素子500bを有している。図12は、トランジスタ400a、トランジスタ400b、及びトランジスタ600のチャネル長方向の断面図である。図12に示すトランジスタ400a、容量素子500a、トランジスタ400b、容量素子500bの構成については、実施の形態3におけるトランジスタ400a、容量素子500a、トランジスタ400b、容量素子500bについての説明を参酌することができる。
本実施の形態では、上記実施の形態で説明した半導体装置又はコンピュータを適用することができる電子機器等について説明する。
[実施例]
Claims (1)
- セルアレイと、
前記セルアレイに電気的に接続された駆動回路と、
前記セルアレイに電気的に接続された第1の増幅回路と、
前記第1の増幅回路に電気的に接続された第2の増幅回路と、を有し、
前記セルアレイは、複数のメモリセルを有し、
前記第1の増幅回路は、前記セルアレイから入力された電位を増幅する機能を有し、
前記第2の増幅回路は、前記第1の増幅回路から入力された電位を増幅する機能を有し、
前記駆動回路、前記第1の増幅回路および前記第2の増幅回路のそれぞれは、前記セルアレイと重なる領域を有する半導体装置。
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