JP2021529439A5 - - Google Patents

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Publication number
JP2021529439A5
JP2021529439A5 JP2021500084A JP2021500084A JP2021529439A5 JP 2021529439 A5 JP2021529439 A5 JP 2021529439A5 JP 2021500084 A JP2021500084 A JP 2021500084A JP 2021500084 A JP2021500084 A JP 2021500084A JP 2021529439 A5 JP2021529439 A5 JP 2021529439A5
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JP
Japan
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layer
oxide
poly
nitride
memory
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JP2021500084A
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English (en)
Japanese (ja)
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JPWO2020009772A5 (https=
JP7502258B2 (ja
JP2021529439A (ja
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JP2021500084A 2018-07-05 2019-06-04 三次元ｆｉｎｆｅｔ構造体を有する分割ゲート不揮発性メモリセル、及びその製造方法 Active JP7502258B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/028,244 2018-07-05
US16/028,244 US10727240B2 (en) 2018-07-05 2018-07-05 Split gate non-volatile memory cells with three-dimensional FinFET structure
PCT/US2019/035459 WO2020009772A1 (en) 2018-07-05 2019-06-04 Split gate non-volatile memory cells with three dimensional finfet structure, and method of making same

Publications (4)

Publication Number Publication Date
JP2021529439A JP2021529439A (ja) 2021-10-28
JP2021529439A5 true JP2021529439A5 (https=) 2022-05-24
JPWO2020009772A5 JPWO2020009772A5 (https=) 2022-05-24
JP7502258B2 JP7502258B2 (ja) 2024-06-18

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JP2021500084A Active JP7502258B2 (ja) 2018-07-05 2019-06-04 三次元ｆｉｎｆｅｔ構造体を有する分割ゲート不揮発性メモリセル、及びその製造方法

Country Status (7)

Country Link
US (2) US10727240B2 (https=)
EP (1) EP3818564A1 (https=)
JP (1) JP7502258B2 (https=)
KR (1) KR102369492B1 (https=)
CN (1) CN112400230B (https=)
TW (1) TWI709247B (https=)
WO (1) WO2020009772A1 (https=)

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US12453136B2 (en) 2022-03-08 2025-10-21 Silicon Storage Technology, Inc. Method of forming a device with planar split gate non-volatile memory cells, planar HV devices, and FinFET logic devices on a substrate

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