JP7502258B2 - 三次元finfet構造体を有する分割ゲート不揮発性メモリセル、及びその製造方法 - Google Patents

三次元finfet構造体を有する分割ゲート不揮発性メモリセル、及びその製造方法 Download PDF

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JP7502258B2
JP7502258B2 JP2021500084A JP2021500084A JP7502258B2 JP 7502258 B2 JP7502258 B2 JP 7502258B2 JP 2021500084 A JP2021500084 A JP 2021500084A JP 2021500084 A JP2021500084 A JP 2021500084A JP 7502258 B2 JP7502258 B2 JP 7502258B2
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fin
fins
top surface
forming
logic
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ジョルバ、セルゲイ
デコベルト、キャサリン
ゾウ、フェン
キム、ジンホ
リウ、シアン
ドー、ナン
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Silicon Storage Technology Inc
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    • H10BELECTRONIC MEMORY DEVICES
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    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0243Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability
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    • H10D30/681Floating-gate IGFETs having only two programming levels
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    • H10D30/6891Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
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    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/0193Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
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    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
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JP2021500084A 2018-07-05 2019-06-04 三次元finfet構造体を有する分割ゲート不揮発性メモリセル、及びその製造方法 Active JP7502258B2 (ja)

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US16/028,244 2018-07-05
US16/028,244 US10727240B2 (en) 2018-07-05 2018-07-05 Split gate non-volatile memory cells with three-dimensional FinFET structure
PCT/US2019/035459 WO2020009772A1 (en) 2018-07-05 2019-06-04 Split gate non-volatile memory cells with three dimensional finfet structure, and method of making same

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JP2021529439A JP2021529439A (ja) 2021-10-28
JP2021529439A5 JP2021529439A5 (https=) 2022-05-24
JPWO2020009772A5 JPWO2020009772A5 (https=) 2022-05-24
JP7502258B2 true JP7502258B2 (ja) 2024-06-18

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US (2) US10727240B2 (https=)
EP (1) EP3818564A1 (https=)
JP (1) JP7502258B2 (https=)
KR (1) KR102369492B1 (https=)
CN (1) CN112400230B (https=)
TW (1) TWI709247B (https=)
WO (1) WO2020009772A1 (https=)

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US12453136B2 (en) 2022-03-08 2025-10-21 Silicon Storage Technology, Inc. Method of forming a device with planar split gate non-volatile memory cells, planar HV devices, and FinFET logic devices on a substrate

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