JP2021515984A - 深い分離を使用するFinFET技術 - Google Patents
深い分離を使用するFinFET技術 Download PDFInfo
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Abstract
Description
Claims (15)
- 第1のP型FinFETトランジスタと、
前記第1のP型FinFETトランジスタに隣接して配設された第1のN型FinFETトランジスタと、
前記第1のN型FinFETトランジスタを隣接した前記第1のP型FinFETトランジスタから横方向に分離する第1の酸化物分離層であって、150nm超過の厚さを有する、第1の酸化物分離層と、を備える、P−N接合。 - 前記第1のP型FinFETトランジスタが、
前記第1のP型FinFETトランジスタの前記第1の酸化物分離層とは反対側に配設された第2の酸化物分離層であって、前記第1の酸化物分離層の厚さの半分未満の厚さを有する、第2の酸化物分離層を備える、請求項1に記載のP−N接合。 - 前記第1の酸化物分離層の前記厚さが前記第2の酸化物分離層の前記厚さの少なくとも3倍である、請求項2に記載のP−N接合。
- 前記P−N接合の積βηρη・βPηPの利得が1未満である、請求項1から3のいずれか一項に記載のP−N接合。
- 前記第1のP型FinFETトランジスタに隣接して配設された第2のP型FinFETトランジスタと、
前記第1のP型FinFETトランジスタを隣接した前記第2のP型FinFETトランジスタから横方向に分離する第2の酸化物分離層であって、前記第1の酸化物分離層の厚さの半分未満の厚さを有する、第2の酸化物分離層と、を更に備える、請求項1に記載のP−N接合。 - 前記第2の酸化物分離層の前記厚さが80nm未満であり、前記第1の酸化物分離層の前記厚さが200nm超過である、請求項5に記載のP−N接合。
- 前記第1のP型FinFETトランジスタと隣接した前記第2のN型FinFETトランジスタとの間に画定される前記第1の酸化物分離層の幅が、前記第1のP型FinFETトランジスタと隣接した前記第2のP型FinFETトランジスタとの間に画定される前記第2の酸化物分離層の幅よりも広い、請求項5に記載のP−N接合。
- 前記第1のN型FinFETトランジスタに隣接して配設された第2のN型FinFETトランジスタと、
前記第1のN型FinFETトランジスタを隣接した前記第2のN型FinFETトランジスタから横方向に分離する第2の酸化物分離層であって、前記第1の酸化物分離層の前記厚さ未満の厚さを有する、第2の酸化物分離層と、を更に備える、請求項1に記載のP−N接合。 - 前記第2の酸化物分離層の前記厚さが80nm未満であり、前記第1の酸化物分離層の前記厚さが200nm超過である、請求項8に記載のP−N接合。
- 前記第1の酸化物分離層の幅が前記第2の酸化物分離層の幅よりも広い、請求項8に記載のP−N接合。
- 前記第1のP型FinFETトランジスタおよび前記第1のN型FinFETトランジスタのうち一方に隣接して配設された第2のFinFETトランジスタであって、前記第1のP型FinFETトランジスタおよび前記第1のN型FinFETトランジスタのうちより近くにある方と同じ型である、第2のFinFETトランジスタと、
前記第2のFinFETトランジスタを前記第1のP型FinFETトランジスタおよび前記第1のN型FinFETトランジスタのうち隣接した一方から横方向に分離する第2の酸化物分離層であって、前記第1の酸化物分離層の前記厚さに実質的に等しい厚さを有する、第2の酸化物分離層と、を更に備える、請求項1に記載のP−N接合。 - P−N接合を形成する方法であって、
半導体基板にエッチングを施して、第1の高アスペクト比のトレンチによって分離された第1の高アスペクト比のフィンおよび第2の高アスペクト比のフィンを含む、複数の高アスペクト比のフィンを形成することと、
前記第1の高アスペクト比のトレンチに酸化物材料を充填することと、
前記第1の高アスペクト比のトレンチを充填している前記酸化物材料の一部分を除去することと、
少なくとも150nmの厚さを有する第1の酸化物分離層を形成するように、前記第1の高アスペクト比のトレンチを充填している前記酸化物材料の前記除去を停止することと、を含む、P−N接合を形成する方法。 - 前記半導体基板にエッチングを施して前記複数の高アスペクト比のフィンを形成することが、
前記第1の高アスペクト比のフィンを前記半導体基板のpドープ領域に形成することと、
前記第2の高アスペクト比のフィンを前記半導体基板のnドープ領域に形成することと、を更に含み、
前記第1および第2の高アスペクト比のフィンが前記第1の高アスペクト比のトレンチによって分離される、請求項12に記載の方法。 - 前記複数の高アスペクト比のフィンのうち第3の高アスペクト比のフィンを、前記第1の高アスペクト比のフィンに隣接した前記半導体基板のpドープ領域に形成することと、
100nm未満の厚さを有する第2の酸化物分離層を、前記第1および第3の高アスペクト比のフィンの間に形成することと、を更に含む、請求項13に記載の方法。 - 前記半導体基板にエッチングされた第2第1の高アスペクト比のトレンチに酸化物材料を充填することと、
前記第2の高アスペクト比のトレンチを充填している前記酸化物材料の一部分を除去することと、
前記第1の酸化物分離層の前記厚さの半分未満の厚さを有する第2の酸化物分離層を形成するように、前記第2の高アスペクト比のトレンチを充填している前記酸化物材料の前記除去を停止することと、を更に含む、請求項13に記載の方法。
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