TWI786270B - 使用深隔離的鰭式場效電晶體技術之緩解方案 - Google Patents

使用深隔離的鰭式場效電晶體技術之緩解方案 Download PDF

Info

Publication number
TWI786270B
TWI786270B TW108105966A TW108105966A TWI786270B TW I786270 B TWI786270 B TW I786270B TW 108105966 A TW108105966 A TW 108105966A TW 108105966 A TW108105966 A TW 108105966A TW I786270 B TWI786270 B TW I786270B
Authority
TW
Taiwan
Prior art keywords
type finfet
isolation layer
thickness
oxide
oxide isolation
Prior art date
Application number
TW108105966A
Other languages
English (en)
Other versions
TW201946273A (zh
Inventor
詹姆士 卡普
麥克 Ｊ 哈特
Original Assignee
美商吉林克斯公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商吉林克斯公司 filed Critical 美商吉林克斯公司
Publication of TW201946273A publication Critical patent/TW201946273A/zh
Application granted granted Critical
Publication of TWI786270B publication Critical patent/TWI786270B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

本文中描述鰭式場效電晶體(FinFET)、P-N接面及用於形成該P-N接面之方法。在一個實例中，描述一種FinFET，其包括由金屬閘極包覆之通道區，該通道區連接源極鰭片與汲極鰭片。第一氧化物隔離層安置於該源極鰭片之第一側上，且第二氧化物隔離層安置於該源極鰭片之第二側上，其中該第二側與該第一側相對。該第二氧化物隔離層具有厚度，該厚度大於該第一氧化物隔離層之厚度。

Description

使用深隔離的鰭式場效電晶體技術之緩解方案
本發明之具體實例大體上係關於FinFET、P-N接面及用於形成P-N接面的方法。更特定而言，本發明之具體實例係關於FinFET及具有深氧化物隔離層之P-N接面。
FinFET歸因於增強在較小奈米節點處電晶體之源極區與汲極區之間流動之電流之控制的能力而已開始在下一代電子裝置中替換傳統平面電晶體。諸如記憶體結構之裝置亦受益於使用FinFET，此係因為FinFET具有較低功率且提供增大之電晶體密度同時使得能夠具有改良之裝置效能。
如同平面電晶體一般，使用FinFET之記憶體結構保持對於單一事件鎖定(single event latch-up；SEL)為敏感的。CMOS技術中之鎖定藉由觸發寄生p-n-p-n矽控整流器(silicon controlled rectifier；SCR)結構而引起。SEL藉由源自沿著入射帶電粒子之軌跡產生之電荷的暫態電流引起。中子為地面應用中SEL的主要原因。針對平面電晶體之習知SEL緩解技術旨在解耦或削弱寄生SCR結構的元素。此類技術通常與對於給定應用可耐受之面積代價(area penalty)相關聯。直至最近，CMOS及基礎SEL裝置物理學兩者已在平面電晶體中一起按比例調整，因此允許針對給定設計流之可預測的SEL結果。然而，此情形已藉由最近引入FinFET技術而改變，此係由於已觀測到，與FinFET中之 SEL事件相關聯的故障率通常高於平面電晶體之故障率。
因此，需要經改良之FinFET。
本文中描述鰭式場效電晶體(FinFET)、P-N接面及用於形成該P-N接面的方法。在一個實例中，描述一種FinFET，其包括鰭片，該鰭片具有藉由金屬閘極包覆之通道區，該通道區連接該鰭片之源極區與汲極區。第一氧化物隔離層安置於該鰭片之第一側上，且第二氧化物隔離層安置於該鰭片之第二側上，其中該第二側與該第一側相對。該第二氧化物隔離層具有厚度，該厚度大於該第一氧化物隔離層之厚度。
在另一實例中，描述一種P-N接面。該P-N接面包括第一P型FinFET、第一N型FinFET及第一氧化物隔離層。該第一N型FinFET鄰近該第一P型FinFET安置。該第一氧化物隔離層側向地分離該第一N型FinFET與該鄰近之第一P型FinFET。該第一氧化物隔離層具有至少150nm之厚度。
在又一實例中，描述一種P-N接面，該P-N接面包括第一P型FinFET、第一N型FinFET及第一氧化物隔離層。該第一N型FinFET鄰近該第一P型FinFET安置。該第一氧化物隔離層側向地分離該第一N型FinFET與該鄰近之第一P型FinFET。該P-N接面具有小於1之βnpn．βpnp乘積增益。
在又一實例中，描述一種用於形成P-N接面之方法，該方法包括：蝕刻一半導體基板以形成複數個高縱橫比鰭片，該複數個高縱橫比鰭片包括藉由第一高縱橫比溝槽分離之第一高縱橫比鰭片與第二高縱橫比鰭片；用氧化物材料填充該第一高縱橫比溝槽；移除填充該第一高縱橫比溝槽之該氧化物材料的一部分；及停止填充該第一高縱橫比溝槽之該氧化物材料之該移除以形成氧化物隔離層，該氧化物隔離層具有至少150nm之厚度。
100:電子裝置
102:N型FinFET
104:P型FinFET
106:半導體基板
108:溝槽
110:溝槽
112:氧化物隔離層
114:氧化物隔離層
150:P-N接面
152:P型井
154:N型井
202:高縱橫比鰭片
206:氧化物罩蓋層
208:金屬閘極
210:汲極區
212:源極區
214:通道區
252:鰭片
256:氧化物罩蓋層
258:金屬閘極
260:汲極區
262:源極區
264:通道區
280:厚度
282:間距/距離
284:厚度
286:距離
300:第一遮罩層
302:開口
304:暴露區
320:第二遮罩層
322:開口
330:第三遮罩層
332:開口
400:方法
因此，可參考具體實例獲得可詳細地理解本發明之以上列舉特徵之方式、上文簡要概述之本發明之更具體描述，其中一些說明於附圖中。然而，應注意，隨附圖式僅說明本發明之典型具體實例且因此不應將其視為限制本發明之範疇，因為本發明可准許其他同等有效之具體實例。
圖1為包括FinFET之具有P-N接面之電子裝置的示意性剖視圖。
圖2為圖1之電子裝置之一部分的等角視圖，該些角視圖說明鄰近N型FinFET安置之P型FinFET。
圖3A至圖3H為在用於形成圖1之電子裝置的序列之不同階段期間的薄膜堆疊之截面視圖，該電子裝置具有鄰近之P型FinFET及N型FinFET。
圖4為用於形成具有鄰近P型FinFET及N型FinFET之電子裝置之方法的方塊圖。
為了促進理解，已使用相同參考數字在可能的情況下指明圖式中共有的相同元件。預期到，一個具體實例之元件可有益地併入於其他具體實例中。
FinFET技術已顯著改良了CMOS效能，且已啟用了至7nm及以上之高階節點之莫耳定律按比例縮小。FinFET之製造需要淺槽隔離(shallow trench isolation；STI)之幾何形狀的顯著改變。STI之用途為電隔離鄰近電晶體。高階平面CMOS電晶體具有在約200至約250nm之範圍內的STI深度。對於FinFET技術，經暴露之矽鰭片藉由回蝕STI形成，此操作致使在約70至約80nm之間的STI深度。FinFET設計在持續之CMOS按比例調整情況下可預期到甚至 進一步的STI深度減小。
自平面至FinFET設計，STI深度之大約3倍之減小已顯著地減小了鄰近pMOS電晶體及NMOS電晶體之源極汲極之間的最小基板路徑。在所有p-n接面係在反向偏壓下時，以上情形在正常CMOS操作期間並不使pMOS/nMOS隔離惡化。然而，鄰近接面之間的減小之基板路徑已發現為在pMOS及nMOS電晶體兩者之接面在SEL暫態期間可經正向偏壓時允許寄生SCR鎖定之觸發。
如上文所論述，習知FinFET歸因於鄰近接面之間的減小之基板路徑為對於SEL事件敏感的。習知FinFET相較於習知平面電晶體歸因於高能量粒子撞擊特定言之對於SEL事件為更敏感的。高能量粒子包括中子、熱中子、α粒子及類似者。詳言之，發明人已觀測到相較於習知平面電晶體，歸因於習知FinFET上之高能量粒子撞擊，需要小10倍之能量要以引起SEL事件。發明人已發現N型FinFET與P型FinFET之間的氧化物隔離厚度與高能量粒子撞擊SEL事件之機率之間的強相依性。因此，本發明在本文中描述用於藉由選擇性地增大氧化物隔離厚度為習知FinFET之氧化物隔離厚度大約2至3倍而改良使用FinFET之電子裝置對於SEL事件之抵抗性的技術。此外，在增大N型FinFET與P型FinFET之間的氧化物隔離厚度同時，相同類型之FinFET之間的較淺氧化物隔離厚度可得以維持。因此，具有對SEL事件之強健抵抗性的電子裝置可在製造成本之最小增大情況下實現。此外，本文中所描述之新穎FinFET相較於傳統FinFET對於SEL事件之敏感度低達10倍，從而所要地逼近且甚至等於平面電晶體之對SEL事件的敏感度。
圖1為電子裝置100之一個實例的示意圖，該電子裝置具有界定於N型FinFET102與鄰近P型FinFET104之間的P-N接面150。在圖1之實例中，電子裝置100經組態為一CMOS裝置。然而，FinFET102、104可經組態以供在包 括N型FinFET102及P型FinFET104兩者的其他類型之裝置中使用。
N型FinFET102及P型FinFET104形成於半導體基板106上。FinFET102、104可藉由相加或相減技術(包括當前已知或將來開發之技術)來形成。
基板106可為矽基板或包含另一合適材料之基板。基板106包括P型井152及N型井154。在描繪於圖1中之實例中，N型井154說明為形成於P型井152上。然而，P型井152可替代地形成於N型井154上，或P型井152可例如在雙槽組態中與N型井154側向隔開。P型井152及N型井154可使用離子植入、擴散或其他合適技術來形成。在一個實例中，P型井152摻雜有磷，而N型井154摻雜有硼。
在描繪於圖1中之實例中，存在形成於P型井152上之至少兩個N型FinFET102。亦存在形成於N型井154上之至少兩個P型FinFET104。N型FinFET102中之一者鄰近P型FinFET104中之一者安置。氧化物隔離層112安置在形成於同一類型之每一鄰近FinFET之間的溝槽108中。舉例而言，氧化物隔離層112安置於每一對鄰近N型FinFET102之間。氧化物隔離層112亦安置於每一對鄰近之P型FinFET104之間。氧化物隔離層114安置在形成於不同類型之鄰近FinFET之間的溝槽110中。舉例而言，氧化物隔離層114安置在鄰近P型FinFET104之N型FinFET102之間。溝槽110之含有氧化物材料之一部分的深度為溝槽108之含有氧化物材料之一部分之深度的至少兩倍，因此使得氧化物隔離層114之厚度為氧化物隔離層112之厚度的至少兩倍。較深溝槽110及較厚氧化物隔離層114跨P-N接面150提供對SEL事件的極優良抵抗性，如下文進一步論述。
P-N接面150之額外細節說明於圖1之電子裝置100之一部分的在圖2中描繪之等角視圖中。如圖2中所示，N型FinFET102包括高縱橫比鰭片202及金屬閘極208，前述兩者自基板106向上延伸。鰭片202可藉由相加式或相減 式技術來形成。在一個實例中，鰭片202可由矽、矽鍺、鍺或III-V族材料形成。鰭片202可視需要覆蓋有薄的氧化物罩蓋層206。
氧化物隔離層112在N型FinFET102之鰭片202之間形成於基板106上。在一個實例中，氧化物隔離層112形成在界定於鰭片202之間的溝槽108中。氧化物隔離層112由以下各者中之一或多者形成：氧化矽、氮化矽、氮氧化矽、經氟摻雜之矽酸鹽玻璃(fluoride-doped silicate glass；FSG)、低k介電質或其他合適材料。類似地，氧化物隔離層114諸如在溝槽110中形成於基板106上，該溝槽界定於N型FinFET102之鰭片202與P型FinFET104之高縱橫比鰭片252之間。氧化物隔離層114可包含適合於用於氧化物隔離層112的相同材料。
金屬閘極208通常具有鰭片形狀，其垂直於基板106之平面且亦垂直於鰭片202之平面。金屬閘極208包圍鰭片202之一部分，分離鰭片202之源極區212與鰭片202之汲極區210。源極區212及汲極區210通常在垂直於基板106之平面延伸的共同平面中對準。源極區212及汲極區210亦垂直於金屬閘極208之平面定向。
金屬閘極208包覆界定於源極區212與汲極區210之間的通道區214。通道區214由與區212、210相同之材料形成，此係由於通道區214為鰭片202之一體式部分。當向金屬閘極208給予能量時，電流自源極區212通過通道區214流至汲極區210。
金屬閘極208由安置於閘極介電材料上方之閘極電極形成。閘極介電材料分離閘極電極與通道區214。閘極電極可為多晶矽、Ta、TiN、TiAlN、TiSiN、TaN、TaAlN、TaSiN、W、WN、Re、Ir、Ru、Mo、Al、Cu、CO、Ni、WN/RuO2、ZrSi2、MoSi2、TaSi2、NiSi2，或其他合適材料。
閘極介電材料可為高K氧化物，諸如鉿類材料。適合於用於閘 極介電材料之鉿類材料的實例包括HfOx、HfSiOx、HfSiON、HfZrO、HfLaO、HfTaO、HfTiO及類似者。替代地，閘極介電材料可為LaO、AlO、ZrO、ZrO2、ZrSiO2、LaSiO、AlSiO、TiO、Ta2O5、Ta2O3、Y2O3、STO、BTO、BaZrO或其他合適材料。在一個實例中，金屬閘極208由安置於HfOx閘極介電材料上方之多晶矽閘極電極形成。
金屬閘極208亦可包括額外層，諸如罩蓋層及界面層。舉例而言，罩蓋層可安置於閘極介電材料與金屬閘極材料之間。罩蓋層可為氧化鑭、LaSiO、氧化錳、氧化鋁，或其他合適材料。罩蓋層可具有範圍介於約3至約10埃的厚度。在另一實例中，界面層可安置於閘極介電材料與通道區214之間。界面層可具有範圍介於約3至約10埃的厚度。界面層可為氧化物，諸如氧化矽或氮氧化矽。替代地，界面層可為氮化矽或其他合適材料。
P型FinFET104包括鰭片252及金屬閘極258，其兩者皆自基板106向上延伸。如同鰭片202一般，鰭片252可藉由相加式或相減式技術來形成。在一個實例中，鰭片252可由矽、矽鍺、鍺或III-V族材料形成。鰭片252可視需要覆蓋有薄的氧化物罩蓋層256。
金屬閘極258通常具有鰭片形狀，其垂直於基板106之平面且亦垂直於鰭片252之平面。金屬閘極258包圍鰭片252之一部分，分離鰭片252之源極區262與鰭片252之汲極區260。源極區262及汲極區260通常在垂直於基板106之平面延伸的共同平面中對準。源極區262及汲極區260亦垂直於金屬閘極258之平面定向。
金屬閘極258包覆界定於源極區262與汲極區260之間的通道區264。通道區264由與區262、260相同之材料形成，此係由於通道區264為鰭片252之一體式部分。當向金屬閘極258給予能量時，電流自源極區262通過通道區264流至汲極區260。
金屬閘極258由安置於閘極介電材料上方之閘極電極形成。閘極介電材料分離閘極電極與通道區264。金屬閘極258類似於如上文參看金屬閘極208所描述構建，且亦可包括額外層，諸如如上文參看金屬閘極208描述之罩蓋層及界面層。
N型FinFET102藉由間距或距離282分離開。在一個實例中，距離282為約42nm。N型FinFET102與P型FinFET104分離開距離286。距離286通常大於距離282以適應更深之氧化物隔離層114的製造。舉例而言，氧化物隔離層114具有大於氧化物隔離層112之厚度280的厚度284。在一個實例中，厚度284為氧化物隔離層112之厚度280的至少約兩倍。在另一實例中，厚度284為氧化物隔離層112之厚度280的至少三倍。預期到，界定溝槽110之寬度與氧化物隔離層112之距離286可經遞減或逐步減低，使得溝槽110之底部處的寬度遠小於溝槽110之氧化物隔離層112與基板106相對地暴露所在的部分處之寬度。舉例而言，溝槽110之底部處的寬度可與距離282相同。
在圖2中描繪之實例中，氧化物隔離層112之厚度280小於約100nm，諸如，介於70至80nm之間。對比而言，氧化物隔離層114之厚度284大於150nm，諸如介於200至250nm之間。以另一方式陳述，氧化物隔離層114之厚度284為氧化物隔離層112之厚度280的至少兩倍。在一個實例中，氧化物隔離層114之厚度284為氧化物隔離層112之厚度280的至少2.5倍。在另一實例中，氧化物隔離層114之厚度284為氧化物隔離層112之厚度280的至少3倍。氧化物隔離層114之深厚度284輔助防止帶電粒子在井152、154之間行進，因此增大對SEL事件之抵抗性。在一個實例中，SEL抵抗性歸因於越過P-N接面150之氧化物隔離層114之厚度284相較於習知FinFET設計之SEL抵抗性大出約10倍。
應瞭解，經選擇以改良對SEL事件之抵抗性的氧化物隔離層114之厚度取決於包含P-N接面150之FinFET的技術節點及臨界尺寸可不同，且預期 到存在於裝置經設計以供使用之環境中的粒子之能級。舉例而言，相較於經設計以用於經硬化之應用或非地面應用，地面應用遭遇具有低得多之能級的粒子。上文描述之氧化物隔離層114之厚度284已證明為適合於針對利用16nm技術節點製造之FinFET的地面應用。諸如在同一技術節點處抵抗較高能量粒子(相對於正常遭遇之地面粒子)需要硬化的航空或其他應用的非地面應用將通常具有較厚氧化物隔離層114。
利用本文中揭示之技術達成的對SEL事件之改良之抵抗性亦可特徵化為相較於使用FinFET技術之習知設計減小寄生SCR的βnpn．βpnp之乘積增益。通常，βnpn及βpnp為寄生SCR之回饋迴路中兩個電晶體的增益。維持βnpn．βpnp乘積增益為小於1將防止鎖定。寄生雙極之β增益為SCR電流路徑中距離的強函數。由於更深STI增大此距離，因此其減小βnpn．βpnp乘積增益。雙極電晶體β增益亦取決於寄生SCR之雙極電晶體中的電流。電流愈高，則βnpn．βpnp乘積增益愈高。由於該些電流與來自離子撞擊之所累積電荷成比例，因此氧化物隔離層114之厚度284可經選擇，使得βnpn．βpnp乘積增益小於預定義設計及輻射環境臨限值，諸如對於常見地面輻射環境小於1。在空間輻射環境中遭遇之較高能量離子撞擊將累積顯著更多之電荷且在寄生雙極電晶體中引起較高電流。此情形又將提昇βnpn．βpnp乘積增益大於1，且相同厚度284可能不足以在此空間輻射環境中防止SEL。較高厚度284可被需要以在此等高能量輻射環境中防止SEL。
圖3A至圖3H為在用於形成圖1之具有鄰近之N型FinFET102與P型FinFET104之電子裝置100的序列之不同階段期間薄膜堆疊的截面視圖。圖4為用於諸如藉由說明於圖3A至圖3H中之序列形成電子裝置，諸如具有鄰近N型FinFET102及P型FinFET104之電子裝置100的方法400之方塊圖。預期到，方法400可用以形成具有P-N接面150之其他電子裝置。
方法400藉由圖案化諸如基板106之基板上之第一遮罩層300而以 操作402開始，諸如在圖3A中所說明。N型井及P型井並未說明於圖3A至圖3H中以避免使該些圖混亂。第一遮罩層300包括複數個開口302，基板106之暴露區304經由該複數個開口暴露以供蝕刻及溝槽形成。第一遮罩層300可為光阻遮罩、硬式遮罩或其組合。
在操作404處，基板106之暴露區304經蝕刻以形成溝槽108，如圖3B中所說明。形成於基板106中之溝槽108藉由乾式(例如，電漿)蝕刻製造。合適蝕刻劑包括鹵素，及含有鹵素之化合物，諸如Cl2、CF4、SF6、NF3及CCl2F2外加其他。可替代地利用濕式蝕刻或其他合適技術。合適濕式蝕刻劑包括硝酸(nitric acid；HNO3)及氫氟酸(hydrofluoric acid；HF)、氫氧化鉀(potassium hydroxide；KOH)、乙二胺鄰苯二酚(ethylenediamine pyrocatechol；EDP)及四甲基銨氫氧化物(tetramethylammonium hydroxide；TMAH)外加其他。
基板106之在溝槽108之間剩餘的材料形成鰭片202、252。鰭片202之間的距離282小於一對鄰近鰭片202、252之間的距離286。距離282可為距離286之至少一半，諸如距離286之至少四分之一。該對鄰近鰭片202、252之間的較大距離286允許溝槽110遠深於溝槽108，藉此促進相對於安置於溝槽108中之氧化物隔離層112較厚的氧化物隔離層114安置於溝槽110中，如在下文描述之方法400之後續操作中進一步說明。
在操作406處，移除第一遮罩層300，如圖3C中所說明。在一個實例中，第一遮罩層300藉由灰化製程諸如藉由暴露至含氧電漿移除或藉由其他合適方法移除。
在操作408處，第二遮罩層320安置於鰭片202、252及溝槽108上。第二遮罩層320經圖案化以形成基板106可經蝕刻經由之開口322，諸如在圖3D中所說明。第二遮罩層320可由諸如參看第一遮罩層300描述之材料及技術 製造並圖案化。
在操作410處，基板106經由第二遮罩層320中之開口322蝕刻以形成溝槽110。如圖3E中所說明，溝槽110深於溝槽108。儘管未按比例繪製，但溝槽110相較於溝槽108深至少兩倍，且相較於溝槽108甚至深達2.5倍或2.5倍以上。另外，溝槽110相較於溝槽108寬至少約兩倍，諸如相較於溝槽108深至少3至4倍。更寬溝槽110促進形成更深溝槽110，使得更多氧化物隔離層可用於來自高能量粒子撞擊的改良之擾亂抵抗性。在蝕刻之後，第二遮罩層320例如在含氧電漿存在情況下藉由灰化或藉由其他合適方法來移除。
在操作412處，溝槽108、110填充有氧化物材料以形成氧化物隔離層112及氧化物隔離層114，如圖3F中所說明。氧化物隔離層112、114可利用旋塗、化學氣相沈積、原子層沈積或其他合適技術來沈積。可例如使用回蝕或化學機械拋光或其他合適平坦化技術使氧化物隔離層112、114之頂面與鰭片202、252之頂面共面。
一旦溝槽108、110填充有氧化物材料，第三遮罩層330便經沈積並圖案化於氧化物材料上以形成開口332。第三遮罩層330可由諸如參看第一遮罩層300描述之材料及技術製造並圖案化。在操作414處，氧化物材料之形成氧化物隔離層112及氧化物隔離層114的一部分經由第三遮罩層330中之開口332蝕刻以設定填充溝槽108之氧化物材料的厚度280以及填充溝槽110之氧化物材料的厚度284，如圖3G中所說明。
在操作416處，移除第三遮罩層330。第三遮罩層330可在含氧電漿存在之情況下藉由灰化或藉由其他合適方法來移除。在操作416之後，金屬閘極208、258形成於鰭片202、252上方，以形成如圖1及圖2中所說明之電晶體102、104。
因此，FinFET102、104，且特定而言，本文中描述之P-N接面 150，相較於習知FinFET及習知P-N接面具有較大SEL抵抗性。由於包含P-N接面150之FinFET102、104相較於習知FinFET具有歸因於高能量粒子撞擊之SEL事件之減小機率，因此諸如CMOS或其他電子裝置之電子裝置100相較於習知電子裝置更穩固。安置於N型FinFET102與P型FinFET104之間的氧化物隔離層114之增大的厚度允許來自衝擊粒子之多數電荷歸因於包含安置於更深溝槽110(相較於溝槽108)中之氧化物隔離層114的相對較厚之材料在圍繞大型區域擴散之前在基板中被耗散，因此又添加針對多位元擾亂之額外保護並使利用P-N接面150之電子裝置100中的不可校正事件之發生最小化。有利地，包含P-N接面150之FinFET102、104比傳統FinFET對SEL事件之敏感度低達10倍，從而合乎需要地逼近並甚至等於平面FinFET之對SEL事件的敏感度。
雖然前述內容是針對本發明的具體實例，但在不脫離本發明之基本範疇的情況下，可設計出本發明之其他及另外具體實例，且由以下申請專利範圍判定本發明之範疇。
102:N型FinFET
104:P型FinFET
106:半導體基板
108:溝槽
110:溝槽
112:氧化物隔離層
114:氧化物隔離層
152:P型井
154:N型井
202:鰭片
206:氧化物罩蓋層
208:金屬閘極
210:汲極區
212:源極區
214:通道區
252:鰭片
256:氧化物罩蓋層
258:金屬閘極
260:汲極區
262:源極區
264:通道區
280:厚度
282:間距/距離
284:厚度
286:距離

Claims (11)

  1. 一種半導體裝置，其包含：P-N接面；第一P型FinFET；第一N型FinFET，其鄰近該第一P型FinFET安置；第一氧化物隔離層，其設置在溝槽中並且側向地分離該第一N型FinFET與鄰近之該第一P型FinFET，在該溝槽中的該第一氧化物隔離層具有從該第一N型FinFET延伸到鄰近之該第一P型FinFET的第一寬度，設置在溝槽中的該第一氧化物隔離層具有第一厚度以及第一寬度；第二氧化物隔離層，其側向地設置鄰近於該第一P型FinFET，該第二氧化物隔離層藉由該第一N型FinFET而與該第一氧化物隔離層分離，該第二氧化物隔離層具有第二厚度以及第二寬度，該第一厚度大於200nm並且該第二厚度小於80nn，且該第一寬度大於該第二寬度；第二N型FinFET，其鄰近該第一N型FinFET安置；及該第二氧化物隔離層側向地分離該第一N型FinFET與鄰近之該第二N型FinFET。
  2. 如請求項1所述之半導體裝置，其中該第一P型FinFET包含：第三氧化物隔離層，其安置於該第一P型FinFET之與該第一氧化物隔離層相對的一側上，該第三氧化物隔離層具有厚度，該厚度小於該第一氧化物隔離層之厚度之一半。
  3. 如請求項2所述之半導體裝置，其中該第一氧化物隔離層之該厚度為該第三氧化物隔離層之該厚度的至少三倍。
  4. 如請求項1所述之半導體裝置，其進一步包含：第二P型FinFET，其被設置鄰近該第一P型FinFET；及 第三氧化物隔離層，其側向地分離該第一P型FinFET與該鄰近之第二P型FinFET，該第三氧化物隔離層具有厚度，該厚度小於該第一氧化物隔離層之厚度之一半。
  5. 如請求項4所述之半導體裝置，其中該第三氧化物隔離層之該厚度小於80nm，且該第一氧化物隔離層之該厚度介於200nm和250nm之間。
  6. 如請求項4所述之半導體裝置，其中界定於該第一P型FinFET與該鄰近之第一N型FinFET之間的該第一氧化物隔離層之該第一寬度大於界定於該第一P型FinFET與該鄰近之第二P型FinFET之間的該第三氧化物隔離層之寬度。
  7. 一種半導體裝置，其包含：P-N接面；第一P型FinFET；第一N型FinFET，其鄰近該第一P型FinFET安置；第二FinFET，其鄰近該第一N型FinFET和該第一P型FinFET中的一者安置，該第二FinFET的類型是與其較接近的該第一N型FinFET和該第一P型FinFET中的一者的類型相同；第一氧化物隔離層，其設置在溝槽中並且側向地分離該第一N型FinFET與鄰近之該第一P型FinFET，該第一氧化物隔離層具有第一厚度和第一寬度，該第一寬度從該第一N型FinFET延伸至鄰近之該第一P型FinFET；第二氧化物隔離層，其側向地設置鄰近於該第一N型FinFET，該第二氧化物隔離層具有第二寬度和第二厚度；以及第三氧化物隔離層，其設置鄰近於該第一P型FinFET，該第二氧化物隔離層或該第三氧化物隔離層中的一者側向地分離該第二FinFET與鄰近之該第一P型FinFET和該第一N型FinFET中的一者，該第一厚度至少為200nm並且該第二 厚度和第三厚度小於80nm，該第二氧化物隔離層具有的厚度是薄於該第一氧化物隔離層的厚度，並且該第一寬度是大於該第二寬度和第三寬度中的每一個。
  8. 一種形成半導體裝置的方法，該半導體裝置具有P-N接面，該方法包含：蝕刻半導體基板以形成多個高縱橫比的鰭片，該多個高縱橫比的鰭片包括由第一高縱橫比溝槽分離之第一高縱橫比鰭片與第二高縱橫比鰭片，該第一高縱橫比溝槽從該第一高縱橫比鰭片和該第二高縱橫比鰭片延伸；以及藉由第二高縱橫比溝槽與該第二高縱橫比鰭片分離的第三高縱橫比鰭片；用絕緣材料填充該第一高縱橫比溝槽和該第二高縱橫比溝槽；移除填充該第一高縱橫比溝槽和該第二高縱橫比溝槽之該絕緣材料的一部分；及停止填充該第一高縱橫比溝槽之該氧化物材料之該移除以形成第一氧化物隔離層，該第一氧化物隔離層具有第一厚度及第一寬度，以及第二氧化物隔離層，該第二氧化物隔離層具有第二厚度和第二寬度，該第一厚度大於200nm並且該第二厚度小於80nm，並且該第一寬度大於該第二寬度，其中蝕刻該半導體基板以形成該多個高縱橫比的鰭片還包括：在該半導體基板之p型摻雜區中形成該第一高縱橫比鰭片；及在該半導體基板之n型摻雜區中形成該第二高縱橫比鰭片，該第一高縱橫比鰭片與該第二高縱橫比鰭片由該第一高縱橫比溝槽分離。
  9. 如請求項8所述之方法，其中形成該第一氧化物隔離層和該第二氧化物隔離層還包括：形成該第一氧化物隔離層的該第一厚度於200nm和250nm之間。
  10. 如請求項8所述之方法，其中用該絕緣材料填充該第一高縱橫比溝槽包括： 從以下各者所組成之群組中選擇至少一種材料來填充該第一高縱橫比溝槽：氧化矽、氮化矽、氮氧化矽、經氟摻雜之矽酸鹽玻璃(FSG)以及低k介電質。
  11. 如請求項8所述之方法，其中該第一高縱橫比鰭片由矽、矽鍺、鍺或III-V族材料形成。
TW108105966A 2018-03-09 2019-02-22 使用深隔離的鰭式場效電晶體技術之緩解方案 TWI786270B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/917,206 2018-03-09
US15/917,206 US10636869B2 (en) 2018-03-09 2018-03-09 Mitigation for FinFET technology using deep isolation

Publications (2)

Publication Number Publication Date
TW201946273A TW201946273A (zh) 2019-12-01
TWI786270B true TWI786270B (zh) 2022-12-11

Family

ID=65686934

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108105966A TWI786270B (zh) 2018-03-09 2019-02-22 使用深隔離的鰭式場效電晶體技術之緩解方案

Country Status (7)

Country Link
US (1) US10636869B2 (zh)
EP (1) EP3762963A1 (zh)
JP (1) JP7446231B2 (zh)
KR (1) KR20200126991A (zh)
CN (1) CN111837232B (zh)
TW (1) TWI786270B (zh)
WO (1) WO2019173033A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11587927B2 (en) * 2019-09-27 2023-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Crown bulk for FinFET device
US20230011474A1 (en) * 2021-07-08 2023-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Fin Bending Reduction Through Structure Design

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130221443A1 (en) * 2012-02-28 2013-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and method of fabricating the same
US20140353715A1 (en) * 2013-06-04 2014-12-04 Semiconductor Manufacturing International (Shanghai) Corporation Finfet device and fabrication method thereof
US20160093714A1 (en) * 2014-09-30 2016-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Ion implantation methods and structures thereof

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4683488A (en) 1984-03-29 1987-07-28 Hughes Aircraft Company Latch-up resistant CMOS structure for VLSI including retrograded wells
US5612242A (en) * 1996-03-11 1997-03-18 United Microelectronics Corp. Trench isolation method for CMOS transistor
US6735110B1 (en) 2002-04-17 2004-05-11 Xilinx, Inc. Memory cells enhanced for resistance to single event upset
US6624654B1 (en) 2002-05-16 2003-09-23 Xilinx, Inc. Methods for implementing circuits in programmable logic devices to minimize the effects of single event upsets
US6617912B1 (en) 2002-06-13 2003-09-09 Xilinx, Inc. Pass gate multiplexer circuit with reduced susceptibility to single event upsets
US6671202B1 (en) 2002-06-13 2003-12-30 Xilinx, Inc. Programmable circuit structures with reduced susceptibility to single event upsets
US6822894B1 (en) 2003-03-25 2004-11-23 Xilinx, Inc. Single event upset in SRAM cells in FPGAs with leaky gate transistors
US7249010B1 (en) 2003-04-03 2007-07-24 Xilinx, Inc. Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA
US7386826B1 (en) 2003-06-24 2008-06-10 Xilinx, Inc. Using redundant routing to reduce susceptibility to single event upsets in PLD designs
US6903571B1 (en) 2003-11-18 2005-06-07 Xilinx, Inc. Programmable systems and devices with multiplexer circuits providing enhanced capabilities for triple modular redundancy
US7064574B1 (en) 2004-06-08 2006-06-20 Xilinx, Inc. PLD memory cells utilizing metal-to-metal capacitors to selectively reduce susceptibility to single event upsets
JPWO2006006438A1 (ja) 2004-07-12 2008-04-24 日本電気株式会社 半導体装置及びその製造方法
US7139190B1 (en) 2005-06-14 2006-11-21 Xilinx, Inc. Single event upset tolerant memory cell layout
US7409610B1 (en) 2005-07-20 2008-08-05 Xilinx, Inc. Total configuration memory cell validation built in self test (BIST) circuit
US7764081B1 (en) 2005-08-05 2010-07-27 Xilinx, Inc. Programmable logic device (PLD) with memory refresh based on single event upset (SEU) occurrence to maintain soft error immunity
US7236000B1 (en) 2005-10-18 2007-06-26 Xilinx, Inc. Method and apparatus for error mitigation of programmable logic device configuration memory
US7701247B1 (en) 2005-10-28 2010-04-20 Xilinx, Inc. Data buffering with readout latency for single-event upset tolerant operation
US7515452B1 (en) 2007-01-03 2009-04-07 Xilinx, Inc. Interleaved memory cell with single-event-upset tolerance
US8065644B1 (en) 2008-03-14 2011-11-22 Xilinx, Inc. Reducing susceptibility of circuit designs to single event upsets
US7994020B2 (en) * 2008-07-21 2011-08-09 Advanced Micro Devices, Inc. Method of forming finned semiconductor devices with trench isolation
JP2011009296A (ja) * 2009-06-23 2011-01-13 Panasonic Corp 半導体装置及びその製造方法
US8384418B1 (en) 2009-09-08 2013-02-26 Xilinx, Inc. Mitigating the effect of single event transients on input/output pins of an integrated circuit device
US8273617B2 (en) * 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8261229B2 (en) 2010-01-29 2012-09-04 Xilinx, Inc. Method and apparatus for interconnect layout in an integrated circuit
US7852107B1 (en) 2010-02-18 2010-12-14 Xilinx, Inc. Single event upset mitigation
US7990173B1 (en) 2010-03-16 2011-08-02 Xilinx, Inc. Single event upset mitigation
US8692381B1 (en) 2011-01-06 2014-04-08 Xilinx, Inc. Integrated circuits with a resistance to single event upset occurrence and methods for providing the same
US8595661B2 (en) * 2011-07-29 2013-11-26 Synopsys, Inc. N-channel and p-channel finFET cell architecture
US8397191B1 (en) 2011-11-07 2013-03-12 Xilinx, Inc. Determining failure rate from circuit design layouts
US8635581B1 (en) 2013-03-15 2014-01-21 Xilinx, Inc. Method and apparatus for single event upset (SEU) detection and correction
US9472672B2 (en) 2013-09-04 2016-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminating fin mismatch using isolation last
CN105097686B (zh) * 2014-04-25 2018-04-13 中芯国际集成电路制造(上海)有限公司 鳍片式场效应晶体管及其制造方法
US9484919B1 (en) 2014-04-30 2016-11-01 Xilinx, Inc. Selection of logic paths for redundancy
US9183338B1 (en) 2014-09-16 2015-11-10 Xilinx, Inc. Single-event upset mitigation in circuit design for programmable integrated circuits
US9483599B1 (en) 2014-09-23 2016-11-01 Xilinx, Inc. Circuit design-specific failure in time rate for single event upsets
US10084080B2 (en) * 2015-03-31 2018-09-25 Stmicroelectronics, Inc. Vertical tunneling FinFET
US9472669B1 (en) * 2015-09-04 2016-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor Fin FET device with epitaxial source/drain
CN106952806A (zh) * 2016-01-07 2017-07-14 中芯国际集成电路制造(上海)有限公司 改善鳍式场效应管性能的方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130221443A1 (en) * 2012-02-28 2013-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and method of fabricating the same
US20140353715A1 (en) * 2013-06-04 2014-12-04 Semiconductor Manufacturing International (Shanghai) Corporation Finfet device and fabrication method thereof
US20160093714A1 (en) * 2014-09-30 2016-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Ion implantation methods and structures thereof

Also Published As

Publication number Publication date
TW201946273A (zh) 2019-12-01
KR20200126991A (ko) 2020-11-09
US20190280086A1 (en) 2019-09-12
CN111837232A (zh) 2020-10-27
EP3762963A1 (en) 2021-01-13
WO2019173033A1 (en) 2019-09-12
CN111837232B (zh) 2024-07-09
JP2021515984A (ja) 2021-06-24
JP7446231B2 (ja) 2024-03-08
US10636869B2 (en) 2020-04-28

Similar Documents

Publication Publication Date Title
US11271089B2 (en) Method for manufacturing semiconductor structure with unleveled gate structure
US20210036128A1 (en) Structure and Formation Method of Semiconductor Device Structure with Gate Stack
US9177951B2 (en) Three-dimensional electrostatic discharge semiconductor device
CN109786330B (zh) 集成电路器件鳍、集成电路及其形成方法
CN101728273B (zh) Pmos元件及其制造方法
US10453741B2 (en) Method for forming semiconductor device contact
CN101661904A (zh) 半导体元件及其制造方法
US20150200295A1 (en) Drain Extended MOS Transistors With Split Channel
CN107346783B (zh) 半导体结构及其制造方法
EP3188245B1 (en) Finfet and fabrication method thereof
TWI786270B (zh) 使用深隔離的鰭式場效電晶體技術之緩解方案
US20140015063A1 (en) Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device
KR20210033388A (ko) 금속 게이트 커팅 공정에서의 잔류물 제거
US20160307897A1 (en) Semiconductor devices
US11699702B2 (en) Input/output devices
TWI662620B (zh) 半導體元件結構及其形成方法
US11658230B2 (en) Method for forming a semiconductor structure including plasma cleaning operations
US20230352483A1 (en) Input/output devices
US20140015062A1 (en) Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device
JP2010183038A (ja) 半導体装置の製造方法