CN105097686B - 鳍片式场效应晶体管及其制造方法 - Google Patents

鳍片式场效应晶体管及其制造方法 Download PDF

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CN105097686B
CN105097686B CN201410169353.4A CN201410169353A CN105097686B CN 105097686 B CN105097686 B CN 105097686B CN 201410169353 A CN201410169353 A CN 201410169353A CN 105097686 B CN105097686 B CN 105097686B
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mask layer
groove
type field
effect transistor
fin type
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CN105097686A (zh
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居建华
张帅
俞少峰
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

本发明公开了一种鳍片式场效应晶体管及其制造方法，制造方法包括以下步骤：在半导体衬底上依次形成第一掩模层和第二掩模层；在第二掩模层上形成第三掩模层；对半导体衬底进行刻蚀，从而去除该区域中的第一掩模层和第二掩模层，并且在半导体衬底上的对应部分中形成第一沟槽；去除第三掩模层；对第一掩模层进行刻蚀，然后去除第二掩模层；对整个半导体衬底进行刻蚀，从而形成鳍片式场效应晶体管的鳍状件以及鳍状件之间的第二沟槽，同时第一沟槽被进一步加深使得第一沟槽深度大于第二沟槽的深度；形成鳍片式场效应晶体管。

Description

鳍片式场效应晶体管及其制造方法
技术领域
本发明涉及半导体领域，具体地说，涉及一种鳍片式场效应晶体管及其制造方法。
背景技术
晶体管是现代集成电路的关键部件。为了满足速度持续加快的要求，晶体管的驱动电流需要持续增大。由于晶体管的驱动电流与晶体管的栅极宽度成正比，所以优选的是具有较大宽度的晶体管。
然而，栅极宽度的增大与减小半导体器件尺寸的要求相冲突。由此，发展出了鳍片式场效应晶体管(FinFET)。典型FinFET的制造带有从衬底延伸的薄“鳍片”(或鳍状件)，例如刻蚀到衬底的硅层中的薄“鳍片”。FinFET的沟道形成在垂直的鳍状件中。将栅极设置在鳍状件上(或包围鳍状件)。栅极可以只布置在沟道的一侧，也可以布置在沟道的两侧。后者使得栅极从沟道的两边控制沟道。FinFET器件具有很多优点，例如降低的短沟道效应和增加的电流流动。但是，当前的FinFET中，为了改善FinFET晶体管中的漏电流，必须改善浅沟道隔离。一种有效的方式是增加浅沟道隔离的深度。然而，随着鳍状件间距的不断减小，很难兼顾到鳍状件的形貌控制和沟道填充。另一种方式是增大器件之间的距离，但这将消耗更大的面积并且仍然难以满足高电压应用的隔离要求。
目前，人们通常采用增加N阱和P阱的离子注入剂量的方式来改善FinFET中的浅沟道隔离。TCAD模拟结果表明，增加离子注入剂量将导致N+/NW和P+/PW的击穿电压(BVD)增大。但是，如果把离子注入剂量增加到1014/cm2以上，将带来诸多问题，例如Rs过低、漏电流增大、电容过高等。
发明内容
本发明的发明人发现上述现有技术中存在问题，并因此针对所述问题中的至少一个问题提出了一种新的技术方案。
本发明的一个目的是提供一种鳍片式场效应晶体管及其制造方法。
根据本发明的一个实施例，一种鳍片式场效应晶体管的制造方法包括以下步骤：在半导体衬底上依次形成第一掩模层和图案化的第二掩模层；在第二掩模层上形成图案化的第三掩模层，其中第三掩模层的图案对应于鳍片式场效应晶体管的鳍状件；对半导体衬底上未受到第三掩模层保护的区域进行刻蚀，从而去除该区域中的第一掩模层和第二掩模层，并且在半导体衬底上的对应部分中形成第一沟槽；去除第三掩模层；对第一掩模层进行刻蚀，然后去除第二掩模层；对整个半导体衬底进行刻蚀，从而形成鳍片式场效应晶体管的鳍状件以及鳍状件之间的第二沟槽，同时第一沟槽被进一步加深使得第一沟槽深度大于第二沟槽的深度；形成鳍片式场效应晶体管，其中各鳍片式场效应晶体管之间通过第一沟槽中的电介质材料彼此隔离，鳍片式场效应晶体管中各个鳍状件之间通过第二沟槽中的电介质材料彼此隔离。
进一步地，所述半导体衬底可以为P型硅衬底，晶向可以为100。
进一步地，所述第一掩模层可以为硬掩膜层，优选地，所述第一掩模层的材料可以为氮化硅。
进一步地，所述第二掩模层可以为硬掩膜层。
进一步地，所述第三掩模层可以为光致抗蚀剂层。
进一步地，可以利用第一掩模层的厚度、刻蚀过程对第一掩模层和半导体衬底的选择性刻蚀速率、以及刻蚀时间来控制所述第一沟槽的深度。
进一步地，形成鳍片式场效应晶体管的步骤还可以包括在半导体衬底中形成N阱和P阱，其中N阱和P阱的边界位于第一沟槽下方并且与第一沟槽的中间对齐。
进一步地，形成鳍片式场效应晶体管的步骤还可以包括通过离子注入在半导体衬底中形成N阱和P阱，所述离子注入的能量范围是25KeV至180KeV。
进一步地，形成鳍片式场效应晶体管的步骤还可以包括通过离子注入在半导体衬底中形成N阱和P阱，所述离子注入的剂量小于1014/cm2。
根据本发明的另一个实施例，一种半导体器件包括多个鳍片式场效应晶体管，其中各个鳍片式场效应晶体管通过第一浅沟槽隔离件彼此隔离，每个鳍片式晶体管中各个鳍状件通过第二浅沟槽隔离件彼此隔离，所述第一浅沟槽隔离件的深度大于第二浅沟槽隔离件的深度。
本发明的一个优点在于，在保持每个FinFET内部各个鳍状件间的沟道隔离深度不变的情况下，各个FinFET之间的沟道隔离深度得到进一步增大，从而改善了器件之间的隔离。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例，并且连同说明书一起用于解释本发明的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本发明，其中：
图1是示出根据本发明的一个实施例的制造鳍片式场效应晶体管的方法的流程图。
图2A-2I是示出根据本发明的一个实施例的制造鳍片式场效应晶体管的示图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
图1示出了根据本发明的一个实施例的制造鳍片式场效应晶体管的方法的流程图。下面将参考图2A-图2F来描述形成鳍片式场效应晶体管的各个步骤。
如图2A所示，首先在半导体衬底201上依次形成第一掩模202和第二掩模203(步骤101)。
这里的半导体衬底201可以包括体硅(掺杂的或未掺杂的)或绝缘体上硅(SOI)衬底的有源层。SOI衬底通常包括半导体材料(比如硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或其组合)的层。也可以使用其它衬底，比如多层衬底、渐变的衬底或混合取向的衬底等。在一个实施例中，半导体衬底201是P型硅衬底，晶向为100。
另外，半导体衬底201还可以包括各种掺杂区域和其它器件(为了更清楚，本申请的图中没有示出)。图中仅仅示意性地例示了半导体衬底的一部分，但这足以充分说明本发明的实施例。
第一硬掩膜层202和第二硬掩膜层203是不同的硬掩膜。这样，在后面的处理步骤中能够单独对第一硬掩膜层202和第二硬掩膜层203之一进行刻蚀。例如，第一硬掩膜层202可以是氮化硅(SiN)，第二硬掩膜层203可以是二氧化硅。
然后，根据鳍片式场效应晶体管的鳍状件的位置对第二掩模层203进行图案化处理，如图2B所示。图2B中形成的第二掩模层203的图案与FinFET的鳍状件位置对应。
接下来，在第二掩模层203上形成图案化的第三掩模层(步骤102)。第三掩模层材料可以是例如光致抗蚀剂。通过常规的曝光、显影等处理过程形成所需要的第三掩模层图案。图2C和图2D分别示意性地示出了第三掩模层图案的截面图和俯视图。如图所示，第三掩模层的图案包括第三掩模层图案206和207。其中，第三掩模层图案206覆盖的区域对应于要形成PMOS的区域，而第三掩模层图案207覆盖的区域对应于要形成NMOS的区域。
接下来，在第三掩模层图案的保护下，对第二掩模层、第一掩模层和半导体衬底进行刻蚀(步骤103)。刻蚀的过程可以分步进行。例如，根据第二掩模层、第一掩模层和半导体衬底材料性质的不同，可以先用一种刻蚀液对第二掩模层进行刻蚀；等到去除第二掩模层后，换用另一种刻蚀液对第一掩模层进行刻蚀；去除第一掩模层后，最后采用又一种刻蚀液对半导体衬底进行刻蚀。当然，根据实际情况，刻蚀过程也可以只采用一种或两种刻蚀剂进行刻蚀，这对于本领域技术人员是熟知的。刻蚀过程可以采用各种刻蚀方法，例如干刻蚀、湿刻蚀或者干刻蚀和湿刻蚀的组合。可以通过含氟气体(例如CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如HBr和/或CHBR3)、含氧气体、含碘气体、其它合适的气体和/或等离子体来进行干刻蚀。
接下来去除第三掩模层(步骤104)。图2E是已经去除了第三掩模层后的半导体器件的截面图。如图所示，被第三掩模层图案206和207覆盖的区域中，半导体衬底201、第一掩模层202和第二掩模层203受到第三掩模层的保护，因而保留下来。而没有被第三掩模层图案覆盖的区域中，在刻蚀作用下，第二掩模层203和第一掩模层202已经被去除，并且该区域中的半导体衬底201也被一定程度地刻蚀，从而初步形成第一沟槽208。在这里，第一沟槽208的深度可以通过控制刻蚀时间、第一掩模层202的厚度、以及刻蚀剂对第一掩模层202和半导体衬底201的选择性刻蚀速率。
接下来，在第二掩模层203的保护下，对第一掩模层202进行刻蚀，从而把鳍片式场效应晶体管的鳍状件图案转移到第一掩模层202上，然后去除第二掩模层203(步骤105)。如图2F所示，半导体衬底201上仅剩下图案化的第一掩模层202。
接下来，在第一掩模层202的保护下，对半导体衬底进行刻蚀，从而形成第二沟槽209，同时还进一步加深了第一沟槽208(步骤106)。如图2G所示，在刻蚀剂作用下，半导体衬底201被整体地刻蚀掉一部分。这样，在第一掩模层202的图案之间的半导体衬底201被刻蚀形成第二沟槽209，而原本已经初步形成的第一沟槽208被进一步加深。
最后，利用图2G所示的结构，进行后续处理过程，最终在半导体衬底上形成鳍片式场效应晶体管(107)。
例如，在根据本发明的一个实施例中，如图2H所示，去除第一掩模层202后，在半导体衬底201上沉积电介质材料，从而使得第一沟槽和第二沟槽中都填充有电介质，然后进行化学机械抛光平坦化(CMP)处理。电介质材料可以为例如氧化硅、氮化硅、氮氧化硅、聚合物等或其它适当的电介质。可以通过例如流动化学气相沉积(FCVD)工艺等来沉积电介质材料。
接下来，可以对电介质进行刻蚀，从而重新露出鳍状件。对于FinFET而言，鳍状件的高度通常为30nm-60nm。如图2I所示，在一个优选实施例中，P阱(PW)和N阱(NW)的边界位于第一沟槽底部的中心。可以通过离子注入来形成P阱和N阱。在本发明中，离子注入的能量需要高于现有FinFET的离子注入能量。例如，在一个优选实施例中，离子注入的能量在25KeV至180KeV之间。另外，离子注入的剂量可以控制在～1013/cm2量级，远小于现有的FinFET离子注入剂量。
进一步的后续处理过程和步骤对于本领域技术人员都是熟知的，为了节省篇幅，本申请就不再赘述。
利用本发明制作的半导体器件中，各个FinFET之间的浅沟槽隔离件的深度大于FinFET内部各个鳍状件之间的浅沟槽隔离件的深度。这样，本发明的方法能够在保持较小的器件间隔的情况下通过增加器件之间浅沟槽隔离的深度，从而改善漏电流或不同器件之间的耐压(击穿)特性。
至此，已经详细描述了根据本发明的制造半导体器件的方法和所形成的半导体器件。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (10)

1.一种鳍片式场效应晶体管的制造方法，包括以下步骤：
在半导体衬底上依次形成第一掩模层和图案化的第二掩模层；
在第二掩模层上形成图案化的第三掩模层，其中第三掩模层的图案对应于鳍片式场效应晶体管的鳍状件；
对半导体衬底上未受到第三掩模层保护的区域进行刻蚀，从而去除该区域中的第一掩模层和第二掩模层，并且在半导体衬底上的对应部分中形成第一沟槽；
去除第三掩模层；
对第一掩模层进行刻蚀，然后去除第二掩模层；
对整个半导体衬底进行刻蚀，从而形成鳍片式场效应晶体管的鳍状件以及鳍状件之间的第二沟槽，同时第一沟槽被进一步加深使得第一沟槽深度大于第二沟槽的深度；
形成鳍片式场效应晶体管，其中各鳍片式场效应晶体管之间通过第一沟槽中的电介质材料彼此隔离，鳍片式场效应晶体管中各个鳍状件之间通过第二沟槽中的电介质材料彼此隔离。
2.根据权利要求1所述的方法，其中所述半导体衬底为P型硅衬底，晶向为100。
3.根据权利要求1所述的方法，其中所述第一掩模层为硬掩膜层。
4.根据权利要求3所述的方法，其中所述第一掩模层的材料为氮化硅。
5.根据权利要求1所述的方法，其中所述第二掩模层为硬掩膜层。
6.根据权利要求1所述的方法，其中所述第三掩模层为光致抗蚀剂层。
7.根据权利要求1所述的方法，其中利用第一掩模层的厚度、刻蚀过程对第一掩模层和半导体衬底的选择性刻蚀速率、以及刻蚀时间来控制所述第一沟槽的深度。
8.根据权利要求1所述的方法，其中形成鳍片式场效应晶体管的步骤还包括在半导体衬底中形成N阱和P阱，其中N阱和P阱的边界位于第一沟槽下方并且与第一沟槽的中间对齐。
9.根据权利要求1所述的方法，其中形成鳍片式场效应晶体管的步骤还包括通过离子注入在半导体衬底中形成N阱和P阱，所述离子注入的能量范围是25KeV至180KeV。
10.根据权利要求1所述的方法，其中形成鳍片式场效应晶体管的步骤还包括通过离子注入在半导体衬底中形成N阱和P阱，所述离子注入的剂量小于1014/cm2。
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