JP7446231B2 - 深い分離を使用するFinFET技術 - Google Patents
深い分離を使用するFinFET技術 Download PDFInfo
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- JP7446231B2 JP7446231B2 JP2020546462A JP2020546462A JP7446231B2 JP 7446231 B2 JP7446231 B2 JP 7446231B2 JP 2020546462 A JP2020546462 A JP 2020546462A JP 2020546462 A JP2020546462 A JP 2020546462A JP 7446231 B2 JP7446231 B2 JP 7446231B2
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Description
Claims (6)
- 基板(106)と、
前記基板(106)上に形成された第1のP型FinFETトランジスタ(104)と、
前記基板(106)上に形成され、前記第1のP型FinFETトランジスタ(104)に隣接して配設された第2のP型FinFETトランジスタ(104)と、
前記基板(106)上に形成され、前記第1のP型FinFETトランジスタ(104)に隣接して配設された第1のN型FinFETトランジスタ(102)と、
前記基板(106)上に形成された第2のN型FinFETトランジスタ(102)と、
前記基板(106)内の前記第1のN型FinFETトランジスタ(102)と前記第1のP型FinFETトランジスタ(104)の間に形成された第1のトレンチ(110)と、
前記基板(106)内の前記第1のP型FinFETトランジスタ(104)と前記第2のP型FinFETトランジスタ(104)の間に形成された第2のトレンチ(108)と、
前記基板(106)内の前記第1のP型FinFETトランジスタ(104)と前記第2のP型FinFETトランジスタ(104)の間に形成された第3のトレンチ(108)と、
前記第1のトレンチ(110)内に配設され、前記第1のN型FinFETトランジスタ(102)を隣接した前記第1のP型FinFETトランジスタ(104)から横方向に分離する、第1の酸化物分離層(114)と、
前記第2のトレンチ(108)内に配設され、前記第1のN型FinFETトランジスタ(102)を隣接した前記第2のN型FinFETトランジスタ(102)から横方向に分離する、第2の酸化物分離層(112)と、
前記第3のトレンチ(108)内に配設され、前記第1のP型FinFETトランジスタ(104)を隣接した前記第2のP型FinFETトランジスタ(104)から横方向に分離する、第3の酸化物分離層(112)と、を備えるP-N接合(150)であって、
前記第1のトレンチ(110)は前記基板(106)内で前記第2のトレンチ(108)および前記第3のトレンチ(108)よりも深く形成され、
前記第1の酸化物分離層(114)は、前記第1のトレンチ(110)内に配設された200nm超過の厚さを有し、
前記第2の酸化物分離層(112)は、前記第2のトレンチ(108)内に配設された80nm未満の厚さを有し、
前記第1の酸化物分離層(114)は、前記第1のN型FinFETトランジスタ(102)から隣接した前記第1のP型FinFETトランジスタ(104)まで延在する第1の幅(286)を有し、
前記第2の酸化物分離層(112)は、前記第1のN型FinFETトランジスタ(102)から隣接した前記第2のN型FinFETトランジスタ(102)まで延在し、前記第1の幅(286)よりも狭い第2の幅(282)を有し、
前記第3の酸化物分離層(112)は、厚さ、幅および材料において前記第2の酸化物分離層(112)と同じ特性を有することを特徴とする、P-N接合(150)。 - 前記第1の酸化物分離層(114)の前記厚さが前記第2の酸化物分離層(112)の前記厚さの少なくとも3倍である、請求項1に記載のP-N接合(150)。
- 前記第1の酸化物分離層(114)の前記厚さが200nmより大きく250nm未満である、請求項1に記載のP-N接合(150)。
- 前記第2の幅(282)が少なくとも第1の幅(286)の半分である、請求項1に記載のP-N接合(150)。
- 前記第2の幅(282)が少なくとも第1の幅(286)の4分の1である、請求項2に記載のP-N接合(150)。
- P-N接合(150)を形成する方法であって、
半導体基板(106)にエッチングを施して、複数のフィン(202、252)を形成すること(410)であって、前記複数のフィン(202、252)が、第1のN型FinFETトランジスタ(102)の一部となる第1のフィン(202)、第2のN型FinFETトランジスタ(102)の一部となる第2のフィン(202)、第1のP型FinFETトランジスタ(104)の一部となる第3のフィン(252)および第2のP型FinFETトランジスタ(104)の一部となる第4のフィン(252)を含み、前記第1および第2のフィン(202)はトレンチによって分離されて第2のトレンチ(108)となり、前記第1のフィン(202)および前記第3のフィン(252)はトレンチによって分離されて第1のトレンチ(110)となり、前記第3および第4のフィン(252)はトレンチによって分離されて第3のトレンチ(108)となる、複数のフィン(202、252)を形成することと、
前記トレンチ(108、110)に酸化物材料を充填すること(412)と、
前記トレンチ(108、110)を充填している前記酸化物材料の一部分を除去すること(416)と、
第1の酸化物分離層(114)および第2の酸化物分離層(112)を形成するために前記酸化物材料の前記除去を停止することであって、前記第1の酸化物分離層(114)は、第1の幅と前記第1のトレンチ(110)内に配設された200nm超過の第1の厚さ(284)を有し、前記第2の酸化物分離層(112)は、前記第2および第3のトレンチ(108)の各々の内に配設された80nm未満の第2の厚さ(280)を有する、前記酸化物材料の前記除去を停止することと、を含み、
前記半導体基板(106)にエッチングを施して、複数のフィン(202、252)を形成することが、
前記第1および第2のフィン(202)を前記半導体基板(106)のpドープ領域に形成することと、
前記第3および第4のフィン(252)を前記半導体基板(106)のnドープ領域に形成することと、を更に含み、
前記第1のトレンチ(110)は前記トレンチ(108)よりも2倍以上幅が広く、前記複数のフィンは前記トレンチ(108)よりも2倍以上高い、方法。
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