JP2021125276A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2021125276A
JP2021125276A JP2020016356A JP2020016356A JP2021125276A JP 2021125276 A JP2021125276 A JP 2021125276A JP 2020016356 A JP2020016356 A JP 2020016356A JP 2020016356 A JP2020016356 A JP 2020016356A JP 2021125276 A JP2021125276 A JP 2021125276A
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Japan
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address information
column
row
circuit
level
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Pending
Application number
JP2020016356A
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English (en)
Japanese (ja)
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JP2021125276A5 (cg-RX-API-DMAC7.html
Inventor
俊哉 長田
Toshiya Osada
俊哉 長田
良和 斉藤
Yoshikazu Saito
良和 斉藤
毅 橋爪
Takeshi Hashizume
毅 橋爪
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Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2020016356A priority Critical patent/JP2021125276A/ja
Priority to US17/158,301 priority patent/US11568908B2/en
Priority to EP21154726.0A priority patent/EP3907738B1/en
Priority to CN202110144294.5A priority patent/CN113284546A/zh
Publication of JP2021125276A publication Critical patent/JP2021125276A/ja
Publication of JP2021125276A5 publication Critical patent/JP2021125276A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/024—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/54—Arrangements for designing test circuits, e.g. design for test [DFT] tools
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1204—Bit line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP2020016356A 2020-02-03 2020-02-03 半導体装置 Pending JP2021125276A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2020016356A JP2021125276A (ja) 2020-02-03 2020-02-03 半導体装置
US17/158,301 US11568908B2 (en) 2020-02-03 2021-01-26 Semiconductor device for detecting failure in address decoder
EP21154726.0A EP3907738B1 (en) 2020-02-03 2021-02-02 Semiconductor memory with detection of address circuit failures
CN202110144294.5A CN113284546A (zh) 2020-02-03 2021-02-02 半导体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020016356A JP2021125276A (ja) 2020-02-03 2020-02-03 半導体装置

Publications (2)

Publication Number Publication Date
JP2021125276A true JP2021125276A (ja) 2021-08-30
JP2021125276A5 JP2021125276A5 (cg-RX-API-DMAC7.html) 2022-07-28

Family

ID=74505068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020016356A Pending JP2021125276A (ja) 2020-02-03 2020-02-03 半導体装置

Country Status (4)

Country Link
US (1) US11568908B2 (cg-RX-API-DMAC7.html)
EP (1) EP3907738B1 (cg-RX-API-DMAC7.html)
JP (1) JP2021125276A (cg-RX-API-DMAC7.html)
CN (1) CN113284546A (cg-RX-API-DMAC7.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024539920A (ja) * 2021-11-22 2024-10-31 シリコン ストーリッジ テクノロージー インコーポレイテッド フラッシュメモリシステムにおけるアドレス障害検出
JP2024541218A (ja) * 2021-11-30 2024-11-08 シリコン ストーリッジ テクノロージー インコーポレイテッド メモリシステムにおけるアドレス障害検出を実行するための階層的ｒｏｍエンコーダシステム

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102936539B1 (ko) * 2021-11-24 2026-03-10 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 데이터 보상 방법
CN116206664B (zh) * 2021-11-30 2025-08-12 硅存储技术股份有限公司 存储器系统中执行地址故障检测的分层rom编码器系统
US12417798B2 (en) * 2022-04-27 2025-09-16 Invention And Collaboration Laboratory Pte. Ltd. Semiconductor memory structure
US20250308578A1 (en) * 2024-04-02 2025-10-02 Nanya Technology Corporation Data verification device and data verification method
US20250383947A1 (en) * 2024-06-17 2025-12-18 Advanced Micro Devices, Inc. Per row activation counting error handling

Citations (5)

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Publication number Priority date Publication date Assignee Title
JPH04341998A (ja) * 1991-05-16 1992-11-27 Nec Corp メモリ回路
JPH06201792A (ja) * 1993-01-06 1994-07-22 Nec Corp テスト回路
US20070002616A1 (en) * 2005-06-15 2007-01-04 Stmicroelectronics S.A. Memory protected against attacks by error injection in memory cells selection signals
US20100107006A1 (en) * 2006-12-07 2010-04-29 Wolfgang Fey Method and Semiconductor Memory With A Device For Detecting Addressing Errors
US20160027529A1 (en) * 2014-07-23 2016-01-28 Freescale Semiconductor, Inc. Address Fault Detection Circuit

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US4912710A (en) * 1988-02-29 1990-03-27 Harris Corporation Self-checking random access memory
JP2002184181A (ja) * 2000-03-24 2002-06-28 Mitsubishi Electric Corp 半導体記憶装置
JP5130570B2 (ja) * 2007-06-19 2013-01-30 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR100915812B1 (ko) 2007-08-14 2009-09-07 주식회사 하이닉스반도체 멀티 칼럼 디코더 스트레스 테스트 회로
JP6115059B2 (ja) * 2012-09-20 2017-04-19 富士通株式会社 半導体記憶装置、及び、情報処理装置
CN103986889B (zh) * 2013-02-08 2017-06-13 豪威科技股份有限公司 用于传感器故障检测的系统及方法
JP6430194B2 (ja) * 2014-09-29 2018-11-28 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP2016184189A (ja) 2015-03-25 2016-10-20 ルネサスエレクトロニクス株式会社 診断プログラム、診断方法および半導体装置
US9824732B2 (en) * 2015-08-03 2017-11-21 Atmel Corporation Memory system with encoding
JP6640030B2 (ja) * 2016-06-06 2020-02-05 ルネサスエレクトロニクス株式会社 メモリマクロおよび半導体集積回路装置
US10141059B2 (en) * 2016-11-30 2018-11-27 Taiwan Semiconductor Manufacturing Co., Ltd. Failure detection circuitry for address decoder for a data storage device
US10553300B2 (en) * 2017-06-09 2020-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of detecting address decoding error and address decoder error detection system
KR102498988B1 (ko) * 2018-06-11 2023-02-14 삼성전자주식회사 페일 어드레스들을 저장하는 레지스터들의 위치들이 병합된 메모리 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04341998A (ja) * 1991-05-16 1992-11-27 Nec Corp メモリ回路
JPH06201792A (ja) * 1993-01-06 1994-07-22 Nec Corp テスト回路
US20070002616A1 (en) * 2005-06-15 2007-01-04 Stmicroelectronics S.A. Memory protected against attacks by error injection in memory cells selection signals
US20100107006A1 (en) * 2006-12-07 2010-04-29 Wolfgang Fey Method and Semiconductor Memory With A Device For Detecting Addressing Errors
US20160027529A1 (en) * 2014-07-23 2016-01-28 Freescale Semiconductor, Inc. Address Fault Detection Circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024539920A (ja) * 2021-11-22 2024-10-31 シリコン ストーリッジ テクノロージー インコーポレイテッド フラッシュメモリシステムにおけるアドレス障害検出
JP7778924B2 (ja) 2021-11-22 2025-12-02 シリコン ストーリッジ テクノロージー インコーポレイテッド フラッシュメモリシステムにおけるアドレス障害検出
JP2024541218A (ja) * 2021-11-30 2024-11-08 シリコン ストーリッジ テクノロージー インコーポレイテッド メモリシステムにおけるアドレス障害検出を実行するための階層的ｒｏｍエンコーダシステム
JP7588764B2 (ja) 2021-11-30 2024-11-22 シリコン ストーリッジ テクノロージー インコーポレイテッド メモリシステムにおけるアドレス障害検出を実行するための階層的ｒｏｍエンコーダシステム

Also Published As

Publication number Publication date
US11568908B2 (en) 2023-01-31
US20210241808A1 (en) 2021-08-05
EP3907738B1 (en) 2024-11-06
EP3907738A1 (en) 2021-11-10
CN113284546A (zh) 2021-08-20

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