CN113284546A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113284546A
CN113284546A CN202110144294.5A CN202110144294A CN113284546A CN 113284546 A CN113284546 A CN 113284546A CN 202110144294 A CN202110144294 A CN 202110144294A CN 113284546 A CN113284546 A CN 113284546A
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CN
China
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row
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output
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Pending
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CN202110144294.5A
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English (en)
Chinese (zh)
Inventor
长田俊哉
齐藤良和
桥爪毅
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Renesas Electronics Corp
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN113284546A publication Critical patent/CN113284546A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/024—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/54—Arrangements for designing test circuits, e.g. design for test [DFT] tools
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1204—Bit line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
CN202110144294.5A 2020-02-03 2021-02-02 半导体装置 Pending CN113284546A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020016356A JP2021125276A (ja) 2020-02-03 2020-02-03 半導体装置
JP2020-016356 2020-02-03

Publications (1)

Publication Number Publication Date
CN113284546A true CN113284546A (zh) 2021-08-20

Family

ID=74505068

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110144294.5A Pending CN113284546A (zh) 2020-02-03 2021-02-02 半导体装置

Country Status (4)

Country Link
US (1) US11568908B2 (cg-RX-API-DMAC7.html)
EP (1) EP3907738B1 (cg-RX-API-DMAC7.html)
JP (1) JP2021125276A (cg-RX-API-DMAC7.html)
CN (1) CN113284546A (cg-RX-API-DMAC7.html)

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* Cited by examiner, † Cited by third party
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US20230162794A1 (en) * 2021-11-22 2023-05-25 Silicon Storage Technology, Inc. Address fault detection in a memory system
KR102936539B1 (ko) * 2021-11-24 2026-03-10 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 데이터 보상 방법
CN116206664B (zh) * 2021-11-30 2025-08-12 硅存储技术股份有限公司 存储器系统中执行地址故障检测的分层rom编码器系统
WO2023101711A1 (en) * 2021-11-30 2023-06-08 Silicon Storage Technology, Inc. Hierarchical rom encoder system for performing address fault detection in a memory system
US12417798B2 (en) * 2022-04-27 2025-09-16 Invention And Collaboration Laboratory Pte. Ltd. Semiconductor memory structure
US20250308578A1 (en) * 2024-04-02 2025-10-02 Nanya Technology Corporation Data verification device and data verification method
US20250383947A1 (en) * 2024-06-17 2025-12-18 Advanced Micro Devices, Inc. Per row activation counting error handling

Citations (11)

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US6452859B1 (en) * 2000-03-24 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Dynamic semiconductor memory device superior in refresh characteristics
US20070002616A1 (en) * 2005-06-15 2007-01-04 Stmicroelectronics S.A. Memory protected against attacks by error injection in memory cells selection signals
JP2009003983A (ja) * 2007-06-19 2009-01-08 Renesas Technology Corp 半導体記憶装置
US20100107006A1 (en) * 2006-12-07 2010-04-29 Wolfgang Fey Method and Semiconductor Memory With A Device For Detecting Addressing Errors
US20140078834A1 (en) * 2012-09-20 2014-03-20 Fujitsu Limited Semiconductor memory device and information processing apparatus
CN103986927A (zh) * 2013-02-08 2014-08-13 豪威科技股份有限公司 用于传感器故障检测的系统及方法
US20160092293A1 (en) * 2014-09-29 2016-03-31 Renesas Electronics Corporation Semiconductor memory device
US20160283339A1 (en) * 2015-03-25 2016-09-29 Renesas Electronics Corporation Diagnostic program, diagnostic method, and semiconductor device
CN107463461A (zh) * 2016-06-06 2017-12-12 瑞萨电子株式会社 存储器宏和半导体集成电路器件
CN108122593A (zh) * 2016-11-30 2018-06-05 台湾积体电路制造股份有限公司 数据存储装置、用于其的地址解码器及其操作方法
CN110580933A (zh) * 2018-06-11 2019-12-17 三星电子株式会社 其中存储故障地址的寄存器的位置被合并的存储器设备

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US4912710A (en) * 1988-02-29 1990-03-27 Harris Corporation Self-checking random access memory
JPH04341998A (ja) * 1991-05-16 1992-11-27 Nec Corp メモリ回路
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US6452859B1 (en) * 2000-03-24 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Dynamic semiconductor memory device superior in refresh characteristics
US20070002616A1 (en) * 2005-06-15 2007-01-04 Stmicroelectronics S.A. Memory protected against attacks by error injection in memory cells selection signals
US20100107006A1 (en) * 2006-12-07 2010-04-29 Wolfgang Fey Method and Semiconductor Memory With A Device For Detecting Addressing Errors
JP2009003983A (ja) * 2007-06-19 2009-01-08 Renesas Technology Corp 半導体記憶装置
US20140078834A1 (en) * 2012-09-20 2014-03-20 Fujitsu Limited Semiconductor memory device and information processing apparatus
CN103986927A (zh) * 2013-02-08 2014-08-13 豪威科技股份有限公司 用于传感器故障检测的系统及方法
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CN107463461A (zh) * 2016-06-06 2017-12-12 瑞萨电子株式会社 存储器宏和半导体集成电路器件
CN108122593A (zh) * 2016-11-30 2018-06-05 台湾积体电路制造股份有限公司 数据存储装置、用于其的地址解码器及其操作方法
CN110580933A (zh) * 2018-06-11 2019-12-17 三星电子株式会社 其中存储故障地址的寄存器的位置被合并的存储器设备

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程瑞娇 等: "一种解决半选择单元干扰问题的SRAM设计方案", 复旦学报(自然科学版), no. 06, 15 December 2016 (2016-12-15) *

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US11568908B2 (en) 2023-01-31
US20210241808A1 (en) 2021-08-05
EP3907738B1 (en) 2024-11-06
JP2021125276A (ja) 2021-08-30
EP3907738A1 (en) 2021-11-10

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