JP2021110932A - 表示パネルとそのリペア方法 - Google Patents
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Abstract
Description
SP1、SP2、SP3、SP4:サブピクセル
EA:発光部
CA:回路部
GL:ゲートライン
DL:データライン
RL:基準電圧ライン
Cst:ストレージキャパシタ
VDDH:横電源ライン
VDDV:縦電源ライン
DT:駆動素子
ST1:第1スイッチ素子
ST2:第2スイッチ素子
RBL:ブランチライン
Claims (20)
- 発光素子からの光が放出される発光領域が定義された複数のピクセル回路と、
ピクセル駆動電圧を前記ピクセル回路に印加する電源ラインと、
前記ピクセル駆動電圧より低い基準電圧が印加される基準電圧ラインと、
前記基準電圧ラインに連結されて一つ以上の前記ピクセル回路に前記基準電圧を印加するブランチラインとを含み、
前記ブランチラインの少なくとも一部が導体化された半導体層を含む、表示パネル。 - 前記ブランチラインの導体化された半導体層の少なくとも一部が、前記ピクセル回路をそれぞれ含むサブピクセルのうち少なくとも一つの発光領域と重なる、請求項1に記載の表示パネル。
- 前記発光素子のアノード電極上に配置されるバンクをさらに含み、
前記バンクは前記アノード電極の一部を露出し前記発光領域が含まれた開口部を定義し、
前記開口部内で前記ブランチラインの導体化された半導体層の少なくとも一部が前記アノード電極と重なる、請求項1に記載の表示パネル。 - 前記電源ラインは、
第1方向に沿って前記ピクセル回路に連結されてピクセル駆動電圧を前記ピクセル回路に印加する第1電源ラインと、
前記第1方向と交差する第2方向に沿って長いラインの形態を有し、前記第1電源ラインに連結された第2電源ラインとを含み、
前記第1電源ラインの少なくとも一部が、
半導体層と金属層が積層された多層構造を有する、請求項1に記載の表示パネル。 - データ電圧が印加される複数のデータラインと、
スキャン信号が印加される複数のゲートラインをさらに含み、
前記ブランチラインの半導体層は、
前記ピクセル回路のうち少なくとも一つの発光領域を第1方向に沿って前記発光領域を横切るライン部と、
前記第1方向と交差する第2方向に沿って前記ライン部から曲がって前記ピクセル回路に連結された分岐部とを含み、
前記ライン部の少なくとも一部が前記導体化された半導体層を含み、
前記ピクセル回路それぞれは一つ以上のトランジスタを含み、
前記分岐部は、半導体領域を有する前記トランジスタの活性層と、前記トランジスタの電極のうち少なくとも一つとを含み、
前記分岐部で前記トランジスタの電極は、導体化された半導体層、または積層された半導体層と金属層を含む、請求項1に記載の表示パネル。 - 前記ブランチラインは、
前記導体化された半導体層を含んだ単層ブランチラインと、
前記単層ブランチラインに連結され、半導体層と金属層が積層された多層構造のブランチラインとを含み、
前記単層ブランチラインの少なくとも一部が前記ピクセル回路のうち少なくとも一つの発光領域と重なり、
前記多層構造のブランチラインが前記ピクセル回路に連結され、
前記多層構造のブランチラインで前記金属層の下の半導体層は不導体の状態の半導体を含み、
前記多層構造のブランチラインは、
隣り合うピクセル回路の間のデータラインと交差する、請求項1に記載の表示パネル。 - 前記基準電圧ラインが前記ブランチラインの半導体層と直接連結された導体化された半導体層を含む、請求項1に記載の表示パネル。
- 前記ブランチラインは、
第1方向に沿って長いライン部と、
第1方向と交差する第2方向に沿って前記ライン部から曲がって前記ピクセル回路に連結された複数の分岐部とを含み、
前記ライン部の少なくとも一部と前記分岐部の少なくとも一部が半導体層と金属層が積層された多層構造を有する、請求項1に記載の表示パネル。 - 前記ライン部と前記分岐部において、前記金属層が前記ピクセル回路をそれぞれ含むサブピクセルのうち少なくとも一つの発光領域を回避する経路に配置される、請求項8に記載の表示パネル。
- 前記ライン部または前記分岐部において、前記半導体層と前記金属層が前記発光素子のアノード電極と重なる、請求項9に記載の表示パネル。
- 前記ライン部は、
前記ピクセル回路をそれぞれ含んだサブピクセルのうち少なくとも一つの発光領域と重なる導体化された半導体層をさらに含む、請求項8に記載の表示パネル。 - 発光素子を駆動する駆動素子、前記駆動素子の下に配置された光遮断層、および前記駆動素子のゲートに連結されたキャパシタをそれぞれが含む複数のピクセル回路と、
ピクセル駆動電圧を前記ピクセル回路に印加する電源ラインと、
前記ピクセル駆動電圧より低い基準電圧が印加される基準電圧ラインと、
前記基準電圧ラインに連結されて一つ以上の前記ピクセル回路に前記基準電圧を印加するブランチラインとを含み、
前記ピクセル回路の断面構造は、
第1金属層と、
前記第1金属層を覆うバッファー層と、
前記バッファー層上に形成されて前記駆動素子の半導体層を覆う絶縁層と、
前記絶縁層上に形成された第2金属層とを含み、
前記第1金属層は、前記駆動素子の光遮断層、および前記キャパシタの下部電極を含み、
前記第2金属層は、前記駆動素子のゲート電極、ソース電極、およびドレイン電極を含み、
前記半導体層は前記駆動素子のチャネルを形成する活性層を含み、
前記ブランチラインの少なくとも一部が前記半導体層と同一平面上に配置される導体化された半導体層を含む、表示パネル。 - 前記ピクセル駆動電圧が前記駆動素子のドレイン電極に印加され、
前記ピクセル回路のそれぞれは、
スキャン信号に応答してデータ電圧を前記駆動素子のゲート電極および前記キャパシタに印加する第1スイッチ素子と、
前記スキャン信号に応答して前記基準電圧を前記駆動素子のソース電極に印加する第2スイッチ素子とをさらに含み、
前記キャパシタは、
前記バッファー層を挟んで前記下部電極と対向する中間電極を含んだ第1キャパシタと、
前記絶縁層を挟んで前記中間電極と対向する上部電極を含んだ第2キャパシタとを含み、
前記中間電極は前記バッファー層上に配置された導体化された半導体パターンを含み、
前記第2金属層は、
前記第1および第2スイッチ素子それぞれのゲート電極、ソース電極、およびドレイン電極をさらに含み、
前記第2金属層は前記キャパシタの上部電極をさらに含む、請求項12に記載の表示パネル。 - 前記ブランチラインは、
前記導体化された半導体層を含んだ単層ブランチラインと、
前記単層ブランチラインに連結され、半導体層と金属層が積層された多層構造のブランチラインとを含み、
前記多層構造のブランチラインに配置された前記金属層が前記第1金属層および前記第2金属層の間で前記半導体層上に配置された、請求項12に記載の表示パネル。 - 前記駆動素子のソース電極が前記絶縁層を貫通するコンタクトホールを通じて前記ブランチラインに連結され、
前記コンタクトホール内で前記ブランチラインの導体化された半導体層または前記ブランチラインの金属層が前記駆動素子のソース電極と連結された、請求項14に記載の表示パネル。 - ピクセル駆動電圧を複数のピクセル回路に印加する電源ライン、前記ピクセル駆動電圧より低い基準電圧が印加される基準電圧ライン、および前記基準電圧ラインに連結されて一つ以上の前記ピクセル回路に前記基準電圧を印加するブランチラインを含む表示パネルのリペア方法において、
前記ブランチラインおよび前記発光素子のアノード電極をレーザービームの波長を変更することなく前記レーザービームを照射して断線させる工程を含み、
前記ブランチラインの少なくとも一部は導体化された半導体層を含む、表示パネルのリペア方法。 - 前記ブランチラインは半導体層と金属層が積層された多層構造をさらに含み、
前記レーザービームが前記ブランチラインの多層構造および前記アノード電極が重なる位置に照射される、請求項16に記載の表示パネルのリペア方法。 - 前記多層構造の半導体層は不導体の状態の半導体層からなる、請求項17に記載の表示パネルのリペア方法。
- 前記ブランチラインの導体化された半導体層の少なくとも一部が、
前記ピクセル回路をそれぞれ含むサブピクセルのうち少なくとも一つの発光領域と重なる、請求項16に記載の表示パネルのリペア方法。 - 前記多層構造の半導体層は酸化物半導体を含み、
前記多層構造の金属層は銅(Cu)、モリチタン(MoTi)のうちいずれか一つまたはこれらの金属が積層された二重金属層を含む、請求項17に記載の表示パネルのリペア方法。
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