JP2021043429A - Iii−v族半導体デバイスの相互接続を作成する方法、及びそれによって作成された相互接続を含むiii−v族半導体デバイス - Google Patents
Iii−v族半導体デバイスの相互接続を作成する方法、及びそれによって作成された相互接続を含むiii−v族半導体デバイス Download PDFInfo
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Abstract
Description
(a)III−V族半導体デバイスの導電部上に第1の厚さを有するポジ型フォトレジスト層を塗布するステップと、
(b)前記ポジ型フォトレジスト層上に第2の厚さを有する像反転性フォトレジスト層を塗布するステップと、
(c)前記像反転性フォトレジスト層及び前記ポジ型フォトレジスト層のそれぞれに、現像可能な形態の第1の部分及び現像不可能な形態の第2の部分が形成されるように、前記像反転性フォトレジスト層及び前記ポジ型フォトレジスト層をパターン露光させて、前記像反転性フォトレジスト層の前記第1の部分及び前記第2の部分が前記ポジ型フォトレジスト層の前記第1の部分及び前記第2の部分の上に重なるステップと、
(d)前記像反転性フォトレジスト層を像反転ベークさせて、前記像反転性フォトレジスト層の前記第1の部分及び前記第2の部分を、現像可能な形態及び現像不可能な形態から、それぞれ現像不可能な形態及び現像可能な形態に変換するステップと、
(e)前記像反転性フォトレジスト層及び前記ポジ型フォトレジスト層をフラッド露光させて、前記ポジ型フォトレジスト層の前記第2の部分を現像不可能な形態から現像可能な形態に変換するステップと、
(f)前記像反転性フォトレジスト層及び前記ポジ型フォトレジスト層のそれぞれの現像可能な形態の前記第2の部分が除去されるように、前記像反転性フォトレジスト層及び前記ポジ型フォトレジスト層を現像させて、前記III−V族半導体デバイスの前記導電部で終結するように下方に延伸する開口部に隣接するアンダーカット側壁を前記像反転性フォトレジスト層に形成するステップと、
(g)前記開口部を介して前記III−V族半導体デバイスの前記導電部上に拡散バリア層を堆積するステップと、
(h)前記開口部を介して前記拡散バリア層上に銅層を堆積して、相互接続を形成するステップと、を含む。
(g1)III−V族半導体デバイス2の導電部22上に10nm〜50nmの範囲の厚さを有する第1のチタン層241をスパッタ堆積するサブステップと、
(g2)第1のチタン層241上に30nm〜60nmの範囲の厚さを有する窒化タングステン層242をスパッタ堆積するサブステップと、
(g3)窒化タングステン層242上に10nm〜50nmの範囲の厚さを有する第2のチタン層243をスパッタ堆積するサブステップとを含む。
21 III−V族半導体コンポーネント
22 導電部
23 誘電体分離層
24 拡散バリア層
25 相互接続
200 ポジ型フォトレジスト層
201 第1の部分
202 第2の部分
241 第1のチタン層
242 窒化タングステン層
243 第2のチタン層
300 像反転性フォトレジスト層
301 第1の部分
302 第2の部分
303 アンダーカット側壁
400 マスク
500 開口部
Claims (15)
- (a)III−V族半導体デバイス(2)の導電部(22)上に第1の厚さを有するポジ型フォトレジスト層(200)を塗布するステップと、
(b)前記ポジ型フォトレジスト層(200)上に第2の厚さを有する像反転性フォトレジスト層(300)を塗布するステップと、
(c)前記像反転性フォトレジスト層(300)及び前記ポジ型フォトレジスト層(200)のそれぞれに、現像可能な形態の第1の部分(301、201)及び現像不可能な形態の第2の部分(302、202)が形成されるように、前記像反転性フォトレジスト層(300)及び前記ポジ型フォトレジスト層(200)をパターン露光させて、前記像反転性フォトレジスト層(300)の前記第1の部分(301)及び前記第2の部分(302)が前記ポジ型フォトレジスト層(200)の前記第1の部分(201)及び前記第2の部分(202)の上に重なるステップと、
(d)前記像反転性フォトレジスト層(300)を像反転ベークさせて、前記像反転性フォトレジスト層(300)の前記第1の部分(301)及び前記第2の部分(302)を、現像可能な形態及び現像不可能な形態から、それぞれ現像不可能な形態及び現像可能な形態に変換するステップと、
(e)前記像反転性フォトレジスト層(300)及び前記ポジ型フォトレジスト層(200)をフラッド露光させて、前記ポジ型フォトレジスト層(200)の前記第2の部分(202)を現像不可能な形態から現像可能な形態に変換するステップと、
(f)前記像反転性フォトレジスト層(300)及び前記ポジ型フォトレジスト層(200)のそれぞれの現像可能な形態の前記第2の部分(302、202)が除去されるように、前記像反転性フォトレジスト層(300)及び前記ポジ型フォトレジスト層(200)を現像させて、前記III−V族半導体デバイス(2)の前記導電部(22)で終結するように下方に延伸する開口部(500)に隣接するアンダーカット側壁(303)を前記像反転性フォトレジスト層(300)に形成するステップと、
(g)前記開口部(500)を介して前記III−V族半導体デバイス(2)の前記導電部(22)上に拡散バリア層(24)を堆積するステップと、
(h)前記開口部(500)を介して前記拡散バリア層(24)上に銅層を堆積して、相互接続(25)を形成するステップと、
を含む、III−V族半導体デバイスの相互接続を作成する方法。 - 前記ステップ(h)の後に、前記像反転性フォトレジスト層(300)及び前記ポジ型フォトレジスト層(200)を除去するステップを更に含む、請求項1に記載の方法。
- 前記ステップ(a)は、500rpm〜4500rpmの範囲の回転速度で、5秒〜60秒の範囲の時間で、前記III−V族半導体デバイス(2)の前記導電部(22)上にポジ型フォトレジストをスピンコーティングすることにより実施される、請求項1または請求項2に記載の方法。
- 前記ステップ(b)は、500rpm〜6000rpmの範囲の回転速度で、5秒〜60秒の範囲の時間で、前記ポジ型フォトレジスト層(200)上に像反転性フォトレジストをスピンコーティングすることにより実施される、請求項1〜請求項3のいずれか一項に記載の方法。
- 前記第2の厚さが前記第1の厚さよりも小さい、請求項1〜請求項4のいずれか一項に記載の方法。
- 前記第1の厚さが2μm〜12μmの範囲にあり、前記第2の厚さが1.14μm〜2.3μmの範囲にある、請求項1〜請求項5のいずれか一項に記載の方法。
- 前記ステップ(c)において、前記パターン露光は、マスク(400)を介して、前記像反転性フォトレジスト層(300)及び前記ポジ型フォトレジスト層(200)を、波長が365nm〜436nmの範囲にある放射線で、0.3秒〜2秒の範囲で露光させることにより実施される、請求項1〜請求項6のいずれか一項に記載の方法。
- 前記ステップ(d)において、前記像反転ベークは、100℃〜120℃の範囲のベーキング温度で、90秒〜150秒の範囲の時間で実施される、請求項1〜請求項7のいずれか一項に記載の方法。
- 前記ステップ(e)において、前記フラッド露光は、前記像反転性フォトレジスト層(300)及び前記ポジ型フォトレジスト層(200)を、波長が365nm〜436nmの範囲にある放射線で、5秒〜15秒の範囲で露光させることにより実施される、請求項1〜請求項8のいずれか一項に記載の方法。
- 前記ステップ(f)において、前記現像は、1.5分〜5分の範囲の時間で、現像液中における撹拌下で実施される、請求項1〜請求項9のいずれか一項に記載の方法。
- 前記ステップ(g)は、
(g1)前記III−V族半導体デバイス(2)の前記導電部(22)上に10nm〜50nmの範囲の厚さを有する第1のチタン層(241)をスパッタ堆積するサブステップと、
(g2)前記第1のチタン層(241)上に30nm〜60nmの範囲の厚さを有する窒化タングステン層(242)をスパッタ堆積するサブステップと、
(g3)前記窒化タングステン層(242)上に10nm〜50nmの範囲の厚さを有する第2のチタン層(243)をスパッタ堆積するサブステップと、を含む、請求項1〜請求項9のいずれか一項に記載の方法。 - 前記ステップ(h)は、電子銃蒸着システムを使用して実施される、請求項1〜請求項11のいずれか一項に記載の方法。
- 前記像反転性フォトレジスト層(300)及び前記ポジ型フォトレジスト層(200)は、リフトオフ方法により除去される、請求項2〜請求項12のいずれかに記載の方法。
- 基板(21)と、
前記基板(21)上に形成された導電部(22)と、
請求項1〜請求項13のいずれか一項に記載の方法によって作成され、前記導電部(22)上に形成された相互接続(25)と、
を含む、III−V族半導体デバイス(2)。 - 前記相互接続(25)は、3μmより大きく且つ10μmを越えない厚さを有する、請求項14に記載のIII−V族半導体デバイス(2)。
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