CN112563191A - 制造iii-v族半导体装置的互连件的方法及iii-v族半导体装置 - Google Patents
制造iii-v族半导体装置的互连件的方法及iii-v族半导体装置 Download PDFInfo
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Abstract
本发明提供一种制造III‑V族半导体装置的互连件的方法及III‑V族半导体装置,该方法包括:利用正型光致抗蚀剂搭配图像反转型(image‑reversible)光致抗蚀剂,于蚀刻后形成下切(undercut)侧壁而围出具有径宽由上自下渐增的开口,而得以自该开口沉积该互连件。本发明能够沉积形成较大厚度的互连件,并且能够避免沉积过程互连件与光致抗蚀剂接触而影响最终形成的互连件的结构。
Description
技术领域
本发明涉及一种III-V族半导体装置及其制造方法,特别是涉及一种制造III-V族半导体装置的互连件的方法,及III-V族半导体装置。
背景技术
以Ⅲ-Ⅴ族(如GaN、GaAs)为材料制成的异质结双极型晶体管(HBT)及高速电子迁移率晶体管(HEMT)等功率元件,由于具有高功率、线性度佳、高截止频率和低损耗功率等优点,因此,被认为是可用于制作高频功率元件的最佳材料。
然而,因为高频功率元件是在大电压、大电流及高频率的操作条件下进行,因此,相较一般元件需要更高的电流承载能力及散热能力,但是目前常用于非高频的功率元件的2微米金属连接导线,其厚度并不足以承受大电压及大电流的操作条件。此外,对高频元件而言,当元件的操作频率提高,若金属连接导线的厚度不足,也会使得元件的寄生阻抗大幅增加而影响元件于高频的操作特性。因此,为了符合高频功率元件的操作特性,如何提供具有更高厚度的金属连接导线则为相关技术开发的重点。
例如,公开号为US2007/0040274A1的美国专利公开一种III-V族半导体装置内连接导线的方法。其主要是以铜为内连接导线金属,通过介电层与光致抗蚀剂的层叠结构,提高可用以沉积铜金属内连接导线的厚度的空间,并利用在铜金属内连接导线与半导体层之间形成氮化钨(WNx)阻障层,以避免厚铜金属导线的铜原子扩散到与该厚铜金属导线连接的半导体层,而得到具有厚铜金属内连接导线的III-V族半导体装置。
发明内容
本发明的目的在于提供一种用于制造III-V族半导体装置的互连件的方法。
本发明的制造III-V族半导体装置的互连件的方法,包含下列步骤。
a)将具有第一厚度的正型光致抗蚀剂层施用于该III-V族半导体装置的导性零件上。
b)将具有第二厚度的图像反转型光致抗蚀剂层施用于该正型光致抗蚀剂层上。
c)使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层接受图案式曝光,以使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层的每一者形成呈可显影型式的第一部分及呈不可显影型式的第二部分,且该图像反转型光致抗蚀剂层的该第一部分及该第二部分分别重叠于该正型光致抗蚀剂层的该第一部分及该第二部分上。
d)使该图像反转型光致抗蚀剂层接受图像反转烘烤,以使该图像反转型光致抗蚀剂层的该第一部分及该第二部分从可显影型式及不可显影型式转换成不可显影型式及可显影型式。
e)使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层接受全曝光,以使该正型光致抗蚀剂层的该第二部分从该不可显影型式转换成该可显影型式。
f)使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层接受显影,而自该图像反转型光致抗蚀剂层该第二部分向下移除至该III-V族半导体装置的导性零件露出而形成开口,其中,该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层共同形成下切侧壁,该下切侧壁围成该开口,而令该开口具有自该图像反转型光致抗蚀剂层向下渐增的径宽。
g)将扩散障壁层经由该开口沉积于该III-V族半导体装置的该导性零件上。
h)将铜层经由该开口沉积于该扩散障壁层上形成该互连件。
较佳地,本发明所述的方法,还包含实施于步骤h)后的步骤i),移除该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层。
较佳地,本发明所述的方法,其中,该步骤a)是通过将正型光致抗蚀剂以从500rpm至4500rpm的旋转速度旋涂于该III-V族半导体装置的该导性零件上持续从5秒至60秒的一段时间而实施。
较佳地,本发明所述的方法,其中,该步骤b)是通过将图像反转型光致抗蚀剂以从500rpm至6000rpm的旋转速度旋涂于该正型光致抗蚀剂层上持续从5秒至60秒的一段时间而实施。
较佳地,本发明所述的方法,其中,该第二厚度小于该第一厚度。
较佳地,本发明所述的方法,其中,该第一厚度介于2μm至12μm,且该第二厚度介于1.14μm至2.3μm。
较佳地,本发明所述的方法,其中,该步骤c)中的该图案式曝光是通过使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层曝置于通过光罩的具有范围从365nm至436nm的波长的辐射,持续照射从0.3秒至2秒的一段时间而实施。
较佳地,本发明所述的方法,其中,该步骤d)中的该图像反转烘烤是于范围从100℃至120℃的烘烤温度持续范围从90秒至150秒的一段时间而实施。
较佳地,本发明所述的方法,其中,该步骤e)中的该全曝光是通过使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层曝置于具有范围从365nm至436nm的波长的辐射,持续照射5秒至15秒的一段时间而实施。
较佳地,本发明所述的方法,其中,该步骤f)中的该显影是于搅拌下的显影剂中持续从1.5分钟至5分钟的一段时间而实施。
较佳地,本发明所述的方法,其中,该步骤g)包含下列子步骤:
g1)将范围从10nm至50nm的厚度的第一钛层喷溅沉积于该III-V族半导体装置的该导性零件上;
g2)将范围从30nm至60nm的厚度的氮化钨层喷溅沉积于该第一钛层上;以及
g3)将范围从10nm至50nm的厚度的第二钛层喷溅沉积于该氮化钨层上。
较佳地,本发明所述的方法,其中,该步骤h)是通过使用电子枪蒸发系统实施。
较佳地,本发明所述的方法,其中,该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层是通过掀离(lift-off)程序移除。
本发明的另一目的在于提供III-V族半导体装置。
本发明的III-V族半导体装置,包含:基材、导性零件,及互连件。
该导性零件形成于该基材上,且该互连件是通过上文所述的方法形成于该导性零件上。
较佳地,本发明所述的III-V族半导体装置,其中,该互连件具有大于3μm,且最高达10μm的厚度。
本发明的有益效果在于:利用图像反转型光致抗蚀剂层及该正型光致抗蚀剂层的层叠及显影特性,通过该正型光致抗蚀剂层增加厚度,而得以提升可用于沉积的开口空间,而得以沉积形成较大厚度的互连件。此外,还可通过显影形成的下切侧避,避免沉积过程互连件与光致抗蚀剂接触,而影响最终形成的互连件的结构。
附图说明
图1是说明本发明方法的该实施例的文字流程图;
图2是辅助说明图1该步骤(a)~(b)的流程示意图;
图3是辅助说明图1该步骤(c)的流程示意图;
图4是辅助说明图1该步骤(d)的流程示意图;
图5是辅助说明图1该步骤(e)的流程示意图;
图6是辅助说明图1该步骤(f)的流程示意图;
图7是辅助说明图1该步骤(g)~(h)的流程示意图;
图8是辅助说明图1该步骤(i)的流程示意图;及
图9是说明由该实施例制得的该III-V族半导体装置的示意图。
具体实施方式
下面结合附图及实施例对本发明进行详细说明:
在本发明被详细描述前,应当注意在以下的说明内容中,类似的组件是以相同的编号来表示。
参阅图9,本发明用于制造互连件的方法的一实施例是可用制造用于如图9所示含有该互连件25的III-V族半导体装置2。利用本发明的方法可制得厚度大于3μm且最高达10μm的厚度的互连件25,而可令该III-V族半导体装置2可更适用于高频元件。
配合参阅图8,该III-V族半导体装置2具有一III-V族半导体元件21、一位于该III-V族半导体元件21的顶面的导性零件22,一覆盖该导性零件22并具有一令该导性零件22的顶面露出的开口的介电绝缘层23、一经由该开口与该导性零件22的顶面连接的互连件25,以及一介于该导性零件22的顶面与该互连件25之间的扩散障壁层24。其中,该互连件25是一由导电性及散热性均佳的铜所构成。
参阅图1,详细地说,本发明用于制造该互连件25的方法的该实施例包含以下步骤。
配合参阅图2,首先进行步骤(a),将具有一第一厚度的一正型光致抗蚀剂层200施用于该III-V族半导体元件21的导性零件22上。
该III-V族半导体元件21可以是一般半导体功率元件,例如由砷化镓(GaAs)为材料构成的异质结晶体管(HBT)、高电子迁移率晶体管(HEMT)、或金属氧化物半导体场效应晶体管(MOSFET)等。该导性零件22是位于该III-V族半导体元件21的顶面用于令该III-V族半导体元件21对外连接的电极。
该步骤(a)是利用旋转涂布(spin coating)方式,将一正型光致抗蚀剂涂布于该导性零件22表面,经干燥后而形成该正型光致抗蚀剂层200。该正型光致抗蚀剂为一般半导体制程常用,于受光(例如UV光)照射后可溶解的光致抗蚀剂。本实施例中该正型光致抗蚀剂是以厚膜正型光致抗蚀剂(厂牌:MERCK,型号:AZ4620)为例说明。
接着,进行步骤(b),将具有一第二厚度的一图像反转型(image-reversible)光致抗蚀剂层300施用于该正型光致抗蚀剂层200上。
详细的说,该图像反转型光致抗蚀剂层300是利用旋转涂布方式将一图像反转型光致抗蚀剂涂布于该正型光致抗蚀剂层200上后经干燥而得。
该图像反转型光致抗蚀剂具有正型光致抗蚀剂特性,并可经由反转烤(reversalback)以及全面曝光(flood exposure)后,将原曝光可溶区域转成不可溶,而具有负光致抗蚀剂特性,并可在显影后于光致抗蚀剂层产生纵向内切的下切侧壁(undercut)。本实施例中该图像反转型光致抗蚀剂是以AZ5214E(厂牌:MERCK)为例说明。
利用该步骤(a)、(b)的旋转涂布参数控制可得到预设厚度的该正型光致抗蚀剂层200及图像反转型光致抗蚀剂层300。
于一些实施例中,该步骤(a)的旋转涂布是在转速500~4500rpm、时间5~60秒的条件下进行,且该正型光致抗蚀剂层200的第一厚度约介于2~12μm,该步骤(b)的旋转涂布是在转速500~6000rpm、时间5~60秒的条件下进行,且该图像反转型光致抗蚀剂层300的第二厚度约介于1.14~2.3μm。较佳地,该正型光致抗蚀剂层200的厚度大于该图像反转型光致抗蚀剂层300的厚度。
接着,配合参阅图3,进行步骤(c),使该图像反转型光致抗蚀剂层300及该正型光致抗蚀剂层200接受图案式曝光(pattern wise exposure)。以使该图像反转型光致抗蚀剂层300及该正型光致抗蚀剂层200的每一者形成呈可显影型式的一第一部分201、301及呈不可显影型式的一第二部分202、302,且该图像反转型光致抗蚀剂层300的该第一部分301及该第二部分302分别重叠于该正型光致抗蚀剂层200的该第一部分201及该第二部分202上。
详细的说,该步骤(c)是利用波长365~436nm的近紫外光(NUV)透过光罩400,持续照射该图像反转型光致抗蚀剂层300及该正型光致抗蚀剂层200约0.3~2秒,令该图像反转型光致抗蚀剂层300及该正型光致抗蚀剂层200于受到光照射的区域转变成可显影型式的该第一部分201、301,而未受到光照射的区域则维持为不可显影型式的该第二部分202、302。图3中,X表示可显影(溶)区域,即为该第一部分201、301。
于本实施例中该步骤(c)是利用波长365nm的UV光,曝光时间1.2秒,进行图案化曝光为例说明。
接着,配合参阅图4,进行步骤(d),使该图像反转型光致抗蚀剂层接受图像反转烘烤(image reversal bake),以令该图像反转型光致抗蚀剂层300的该第一部分301从该可显影型式转换成该不可显影型式。
详细的说,该步骤(d)是将经过图案式曝光后的光致抗蚀剂于100~120℃下进行反转烘烤约90~150秒,令该图像反转型光致抗蚀剂层300的第一部分301于烘烤后从可显影型式转换成不可显影型式,该第二部分302则从不可显影型式转换成可显影型式。而该正型光致抗蚀剂层200因不受反转烘烤影响,因此,其第一部分201及第二部分202,仍分别维持为可显影型式及不可显影型式。图4中,X表示可显影(溶)区域。于本实施例中,该步骤(d)是在110℃、烘烤时间120秒的条件下进行反转烘烤。
接着,配合参阅图5,进行步骤(e),使该图像反转型光致抗蚀剂层300及该正型光致抗蚀剂层200接受全曝光(flood exposure),以使该正型光致抗蚀剂层200的该第二部分202,从该不可显影型式转换成该可显影型式。
详细的说,该步骤(e)是将经过反转烘烤的光致抗蚀剂,曝置于具有波长范围从365nm至436nm的辐射照射下,持续照射5秒至15秒接受全曝光,从而令该正型光致抗蚀剂层200于该步骤(c)中未照射到紫外光而呈不可显影型式的该第二部分202,于该步骤(e)照光后转变成可显影型式。也就是说,经过该步骤(e)后,该图像反转型光致抗蚀剂层300的该第一部分301及该第二部分302分别呈不可显影型式及可显影型式,而该正型光致抗蚀剂层200该第一部分201及第二部分202则均为可显影型式。
然后,配合参阅图6,进行步骤(f),使该图像反转型光致抗蚀剂层300及该正型光致抗蚀剂层200接受显影,自该图像反转型光致抗蚀剂层300的该第二部分302向下移除至该导性零件22露出而形成一开口500。
详细的说,该步骤(f)是利用显影液自该图像反转型光致抗蚀剂层300的第二部分302向下移除该图像反转型光致抗蚀剂层300的第二部分302以及该正型光致抗蚀剂层200的第二部分202,并于显影过程令该图像反转型光致抗蚀剂层300及该正型光致抗蚀剂层200共同形成一下切侧壁(undercut)303,该下切侧壁303会围成该开口500,而令显影后形成的该开口500具有自该图像反转型光致抗蚀剂层300向下渐增的径宽。
接着,配合参阅图7,进行步骤(g),将一扩散障壁层24经由该开口500沉积于该III-V族半导体元件21的该导性零件22上。
详细的说,该步骤(g)是经由该开口500先沉积该扩散障壁层24,以避免后续预形成的厚铜层的铜原子扩散至该半导体元件21,而影响该半导体元件21特性的问题,且该扩散障壁层24可视需求及后续制程而为单层或多层结构。于本实施例中,是以该扩散障壁层24为多层结构为例说明。
详细的说,该步骤(g)是包含以下子步骤。
首先,进行子步骤(g1),利用喷溅方式于该导性零件22上形成一层由钛构成的第一钛层241,且该第一钛层241的厚度介于10nm至50nm。
接着,进行子步骤(g2),利用喷溅方式于该第一钛层241上形成一层由氮化钨构成的氮化钨层242,且该氮化钨层242的厚度介于30nm至60nm。
最后,进行子步骤(g3),利用喷溅方式于该氮化钨层242上形成一层由钛构成的第二钛层243,且该第二钛层243的厚度介于10nm至50nm,而得到该扩散障壁层31。
然后,续配合参阅图7,进行步骤(h),自该开口500于该扩散障壁层24上沉积一层由铜为材料构成并具有预定厚度的铜层,而形成该互连件25。于沉积该厚铜层的过程中,因为该步骤(g)形成的该开口500为具有向下渐增的径宽,因此,于沉积过程中可维持令该厚铜层不与该下切侧壁303接触,而可令最终形成于该开口500内的该互连件25可与该下切侧壁303形成间距而不相接触。
于一些实施例中,该步骤(h)的铜层是利用电子枪蒸镀方式沉积而得。
最后,配合参阅图8、9,进行该步骤(i),将该图像反转型光致抗蚀剂层300及该正型光致抗蚀剂层200利用掀离(lift-off)程序移除,即可完成该互连件25的制作,而得到如图9所示具有该互连件25的III-V族半导体装置2。
综上所述,本发明利用正型光致抗蚀剂跟图像反转型光致抗蚀剂搭配,让正型光致抗蚀剂以厚膜方式先形成一具有较大预定厚度的正型光致抗蚀剂层200,通过该正型光致抗蚀剂层200增加厚度,而得以提升后续可用于沉积该连接件25的空间,而可得到具较大厚度的互连件25。并利用形成于该正型光致抗蚀剂层200上的图像反转型光致抗蚀剂层300的绕射特性,而可在经图像反转后将光致抗蚀剂上端接受曝光剂量较多的光致抗蚀剂保留下来,因此,于显影后可形成负侧壁角度(即下切侧壁),而得到上窄下宽形态的开口500,利用该开口500上窄下宽的特性,使得后续沉积该厚铜层时,可避免铜层与该下切侧壁303接触,因此,可更易移除该图像反转型光致抗蚀剂层300及该正型光致抗蚀剂层200,而不影响该连接件25的结构及该连接件25结构的完整性,故确实可达成本发明的目的。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
Claims (15)
1.一种制造III-V族半导体装置的互连件的方法,其特征在于,包含下列步骤:
a)将具有第一厚度的正型光致抗蚀剂层施用于该III-V族半导体装置的导性零件上;
b)将具有第二厚度的图像反转型光致抗蚀剂层施用于该正型光致抗蚀剂层上;
c)使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层接受图案式曝光,以使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层的每一者形成呈可显影型式的第一部分及呈不可显影型式的第二部分,且该图像反转型光致抗蚀剂层的该第一部分及该第二部分分别重叠于该正型光致抗蚀剂层的该第一部分及该第二部分上;
d)使该图像反转型光致抗蚀剂层接受图像反转烘烤,以使该图像反转型光致抗蚀剂层的该第一部分及该第二部分从可显影型式及不可显影型式转换成不可显影型式及可显影型式;
e)使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层接受全曝光,以使该正型光致抗蚀剂层的该第二部分从该不可显影型式转换成该可显影型式;
f)使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层接受显影,而自该图像反转型光致抗蚀剂层该第二部分向下移除至该III-V族半导体装置的导性零件露出而形成开口,其中,该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层共同形成下切侧壁,该下切侧壁围成该开口,而令该开口具有自该图像反转型光致抗蚀剂层向下渐增的径宽;
g)将扩散障壁层经由该开口沉积于该III-V族半导体装置的该导性零件上;以及
h)将铜层经由该开口沉积于该扩散障壁层上形成该互连件。
2.根据权利要求1所述的方法,其特征在于,还包含实施于步骤h)后的步骤i),该步骤i)用于移除该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层。
3.根据权利要求1所述的方法,其特征在于,该步骤a)是通过将正型光致抗蚀剂以从500rpm至4500rpm的旋转速度旋涂于该III-V族半导体装置的该导性零件上持续从5秒至60秒的一段时间而实施。
4.根据权利要求1所述的方法,其特征在于,该步骤b)是通过将图像反转型光致抗蚀剂以从500rpm至6000rpm的旋转速度旋涂于该正型光致抗蚀剂层上持续从5秒至60秒的一段时间而实施。
5.根据权利要求1所述的方法,其特征在于,该第二厚度小于该第一厚度。
6.根据权利要求1所述的方法,其特征在于,该第一厚度介于2μm至12μm,且该第二厚度介于1.14μm至2.3μm。
7.根据权利要求1所述的方法,其特征在于,该步骤c)中的该图案式曝光是通过使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层曝置于通过光罩的具有范围从365nm至436nm的波长的辐射,持续照射从0.3秒至2秒的一段时间而实施。
8.根据权利要求1所述的方法,其特征在于,该步骤d)中的该图像反转烘烤是于范围从100℃至120℃的烘烤温度持续范围从90秒至150秒的一段时间而实施。
9.根据权利要求1所述的方法,其特征在于,该步骤e)中的该全曝光是通过使该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层曝置于具有范围从365nm至436nm的波长的辐射,持续照射5秒至15秒的一段时间而实施。
10.根据权利要求1所述的方法,其特征在于,该步骤f)中的该显影是通过于搅拌下的显影剂中持续从1.5分钟至5分钟的一段时间而实施。
11.根据权利要求1所述的方法,其特征在于,该步骤g)包含下列子步骤:
g1)将范围从10nm至50nm的厚度的第一钛层喷溅沉积于该III-V族半导体装置的该导性零件上;
g2)将范围从30nm至60nm的厚度的氮化钨层喷溅沉积于该第一钛层上;以及
g3)将范围从10nm至50nm的厚度的第二钛层喷溅沉积于该氮化钨层上。
12.根据权利要求1所述的方法,其特征在于,该步骤h)是通过使用电子枪蒸发系统实施。
13.根据权利要求1所述的方法,其特征在于,该图像反转型光致抗蚀剂层及该正型光致抗蚀剂层是通过掀离程序移除。
14.一种III-V族半导体装置,其特征在于,包含:
基材;
导性零件,其形成于该基材上;以及
互连件,其通过如权利要求1所述的方法形成于该导性零件上。
15.根据权利要求14所述的III-V族半导体装置,其特征在于,该互连件具有大于3μm,且最高达10μm的厚度。
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