JP2021010027A - 半導体装置および半導体装置の製造方法 - Google Patents
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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Abstract
Description
本発明にかかる半導体装置は、ワイドバンドギャップ半導体を用いて構成される。実施の形態1においては、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いて作製された炭化珪素半導体装置について、MOSFETを例に説明する。図1は、実施の形態1にかかる半導体装置の構造を示す断面図である。
次に、実施の形態1にかかる半導体装置の製造方法について、例えば1200Vの耐圧クラスのMOSFETを作製する場合を例に説明する。図2および図3は、実施の形態にかかる半導体装置の製造途中の状態を示す断面図である。まず、例えば2.0×1019/cm3の不純物濃度となるように窒素(N)などのn型不純物(ドーパント)をドーピングした炭化珪素単結晶のn+型炭化珪素基板(半導体ウエハ)1を用意する。n+型炭化珪素基板1のおもて面は、例えば<11−20>方向に4度程度のオフ角を有する(0001)面であってもよい。次に、n+型炭化珪素基板1のおもて面に、例えば1.0×1016/cm3の不純物濃度となるように窒素などのn型不純物をドーピングしたn-型炭化珪素層2を例えば10μmの厚さでエピタキシャル成長させる。
図4は、本発明の実施の形態2にかかる半導体装置の構造を示す断面図である。図4に示すように、実施の形態2にかかる炭化珪素半導体装置は、エッジ終端領域30において、n-型炭化珪素層2の表面に、p+型ベース領域3から離れ、互いに離れた複数のp型半導体領域36を有するFLR構造を設けている。p型半導体領域36は、活性領域20の周囲を囲む同心円状に、段差34によりp型炭化珪素層6の厚さが薄くなった部分と対向するn-型炭化珪素層2の表面に設けられている。
次に、実施の形態2にかかる半導体装置の製造方法について説明する。まず、実施の形態1と同様に、n-型炭化珪素層2を形成する工程から、p+型ベース領域3を選択的に形成する工程までを順に行う。
2 n-型炭化珪素層
3 p+型ベース領域
5 n型領域
6 p型炭化珪素層
7 n+型ソース領域
8 p++型コンタクト領域
9 ゲート絶縁膜
10 ゲート電極
11 層間絶縁膜
12 ソース電極
13 ソース電極パッド
14 ドレイン電極
15 トレンチ
20 活性領域
30 エッジ終端領域
31、34、35 段差
32 JTE構造
33 n+型半導体領域
36 p型半導体領域
40 炭化珪素基体
Claims (5)
- シリコンよりもバンドギャップの広い半導体からなる第1導電型の半導体基板に設けられた、主電流が流れる活性領域と、
前記活性領域の周囲を囲む終端領域と、
前記半導体基板のおもて面に設けられ、かつ、前記活性領域から前記終端領域に延在する、シリコンよりもバンドギャップが広い半導体からなる第2導電型の半導体層と、
を備え、
前記半導体層は、前記終端領域に延在した領域に、一つまたは複数の段差を備え、前記段差により、前記活性領域から外側に配置されるほど厚さが薄くなっており、
前記終端領域は、前記活性領域の周囲を囲む同心円状に、前記段差により、厚さが薄くなっている前記半導体層の部分と深さ方向に対向する位置に、シリコンよりもバンドギャップが広い半導体からなる、互いに離して配置された複数の第2導電型の半導体領域をさらに有することを特徴とする半導体装置。 - 前記複数の第2導電型の半導体領域は、均等に配置し、活性領域から外側に配置するほど不純物濃度が低くなっていることを特徴とする請求項1に記載の半導体装置。
- 前記複数の第2導電型の半導体領域は、該第2導電型の半導体領域の間の幅が同一で、当該第2導電型の半導体領域の幅が活性領域から外側に配置するほど狭くなっていることを特徴とする請求項1に記載の半導体装置。
- 前記複数の第2導電型の半導体領域は、該第2導電型の半導体領域の幅が同一で、当該第2導電型の半導体領域の間の幅が活性領域から外側に配置するほど広くなっていることを特徴とする請求項1に記載の半導体装置。
- シリコンよりもバンドギャップの広い半導体からなる第1導電型の半導体基板に設けられた、主電流が流れる活性領域と、
前記活性領域の周囲を囲む終端領域と、
前記半導体基板のおもて面に設けられ、かつ、前記活性領域から前記終端領域に延在する、シリコンよりもバンドギャップが広い半導体からなる第2導電型の半導体層と、を備えた半導体装置の製造方法であって、
前記活性領域から外側に配置されるほど前記半導体層の厚さを薄くする一つまたは複数の段差を、前記終端領域に延在した領域に形成する工程と、
前記終端領域に、前記活性領域の周囲を囲む同心円状に、前記段差により、厚さが薄くなっている前記半導体層の部分と深さ方向に対向する位置に、シリコンよりもバンドギャップが広い半導体からなる、互いに離して配置された複数の第2導電型の半導体領域を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。
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WO2016104264A1 (ja) * | 2014-12-25 | 2016-06-30 | 富士電機株式会社 | 半導体装置 |
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