JP2020537343A - マイクロ電子デバイスのための保護層を備えたダイ取り付け表面銅層 - Google Patents
マイクロ電子デバイスのための保護層を備えたダイ取り付け表面銅層 Download PDFInfo
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- JP2020537343A JP2020537343A JP2020519728A JP2020519728A JP2020537343A JP 2020537343 A JP2020537343 A JP 2020537343A JP 2020519728 A JP2020519728 A JP 2020519728A JP 2020519728 A JP2020519728 A JP 2020519728A JP 2020537343 A JP2020537343 A JP 2020537343A
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- copper
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Abstract
Description
Claims (20)
- マイクロ電子デバイスであって、
構成要素表面と、前記構成要素表面とは反対側に位置するダイ取り付け表面とを有する基板、
前記構成要素表面に近接して位置する構成要素、
前記ダイ取り付け表面上の銅含有層であって、前記ダイ取り付け表面の横方向外周から窪んでいる、前記銅含有層、及び
前記銅含有層上のダイ取り付け材料、
を含み、
前記銅含有層が前記ダイ取り付け材料によってパッケージ部材に取り付けられる、
マイクロ電子デバイス。 - 請求項1に記載のマイクロ電子デバイスであって、前記銅含有層が5ミクロン〜10ミクロンの厚みである、マイクロ電子デバイス。
- 請求項1に記載のマイクロ電子デバイスであって、前記銅含有層と前記ダイ取り付け表面との間に中間層を更に含む、マイクロ電子デバイス。
- 請求項3に記載のマイクロ電子デバイスであって、前記中間層がチタンを含む、マイクロ電子デバイス。
- 請求項1に記載のマイクロ電子デバイスであって、前記銅含有層と前記ダイ取り付け材料との間に保護金属層を更に含み、前記保護金属層が、錫、銀、及びニッケルからなる群から選択される少なくとも1つの金属を含む、マイクロ電子デバイス。
- 請求項1に記載のマイクロ電子デバイスであって、前記ダイ取り付け材料がはんだを含む、マイクロ電子デバイス。
- 請求項1に記載のマイクロ電子デバイスであって、前記基板が15ミクロン〜300ミクロンの厚みである、マイクロ電子デバイス。
- マイクロ電子デバイスを形成する方法であって、
構成要素面と、前記構成要素面とは反対側に位置するダイ取り付け面とを有する基板ウェハであって、前記構成要素面に近接する前記マイクロ電子デバイスの構成要素を含む前記基板ウェハを提供すること、
前記ダイ取り付け面において前記基板ウェハから材料を除去すること、
前記ダイ取り付け面上に銅含有層を形成することであって、前記銅含有層が前記マイクロ電子デバイスのためのエリアの横方向外周から窪まされること、及び
めっきプロセスによって前記銅含有層上に保護金属層を形成すること、
を含む、方法。 - 請求項8に記載の方法であって、前記保護金属層が、錫、銀、及びニッケルからなる群から選択される少なくとも1つの金属を含む、方法。
- 請求項8に記載の方法であって、
前記基板ウェハから前記材料を取り除く前の前記基板ウェハの厚みが300ミクロンより大きく、
前記基板ウェハから前記材料を取り除いた後の前記基板ウェハの厚みが300ミクロン未満である、
方法。 - 請求項8に記載の方法であって、前記銅含有層を形成することが、
前記ダイ取り付け面にシード層を形成すること、
前記シード層上にめっきマスクを形成することであって、前記シード層が前記銅含有層のためのエリアを露出させること、
めっきプロセスによって前記めっきマスクにより露出された箇所の前記シード層上の銅をめっきすること、及び
前記めっきマスクを取り除くこと、
を含む、方法。 - 請求項11に記載の方法であって、前記銅含有層が5ミクロン〜10ミクロンの厚みである方法。
- 請求項11に記載の方法であって、前記銅含有層を形成するのと同時に、前記構成要素面上に銅含有ピラーの少なくとも一部を形成することを更に含む、方法。
- 請求項8に記載の方法であって、前記銅含有層を形成することが、前記ダイ取り付け面上に銅含有材料を堆積させるアディティブ法を含む、方法。
- 請求項8に記載の方法であって、前記基板ウェハから前記材料を除去した後であり前記銅含有層を形成する前に、前記ダイ取り付け面上に中間層を形成することを更に含み、前記銅含有層が前記中間層上に形成される、方法。
- マイクロ電子デバイスを形成する方法であって、
構成要素表面と、前記構成要素表面とは反対側に位置するダイ取り付け表面とを有する、300ミクロン未満の厚みの基板を提供すること、及び
ダイ取り付け材料でパッケージ部材に前記基板を取り付けること、
を含み、
前記基板が、前記構成要素表面に近接する構成要素を含み、前記基板が、前記ダイ取り付け表面上に銅含有層を有し、前記銅含有層が前記ダイ取り付け表面の横方向外周から窪んでおり、前記基板が前記銅含有層上に保護金属層を有し、前記銅含有層が、前記ダイ取り付け表面と前記保護金属層との間にあり、
前記銅含有層が、前記ダイ取り付け材料によって前記パッケージ部材に取り付けられる、
方法。 - 請求項16に記載の方法であって、前記基板を前記パッケージ部材に取り付ける前に、前記保護金属層を取り除くことを更に含む、方法。
- 請求項16に記載の方法であって、前記銅含有層が5ミクロン〜10ミクロンの厚みである方法。
- 請求項16に記載の方法であって、前記ダイ取り付け材料がはんだを含む、方法。
- 請求項19に記載の方法であって、前記基板を前記パッケージ部材に取り付けることが、はんだリフロープロセスを含む、方法。
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US201762568463P | 2017-10-05 | 2017-10-05 | |
US62/568,463 | 2017-10-05 | ||
US15/984,343 | 2018-05-19 | ||
US15/984,343 US10566267B2 (en) | 2017-10-05 | 2018-05-19 | Die attach surface copper layer with protective layer for microelectronic devices |
PCT/US2018/054415 WO2019071006A1 (en) | 2017-10-05 | 2018-10-04 | COPPER LAYER WITH CHIP FASTENING SURFACE WITH PROTECTIVE LAYER FOR MICROELECTRONIC DEVICES |
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US10566267B2 (en) | 2020-02-18 |
US20190109074A1 (en) | 2019-04-11 |
WO2019071006A1 (en) | 2019-04-11 |
CN111344860A (zh) | 2020-06-26 |
US20200185309A1 (en) | 2020-06-11 |
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