JP2020519029A - 露出した端子領域を有する樹脂封止パワー半導体モジュール - Google Patents
露出した端子領域を有する樹脂封止パワー半導体モジュール Download PDFInfo
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Abstract
Description
本発明は、パワー半導体モジュール、パワー半導体モジュールアセンブリ、およびパワー半導体モジュールの製造方法に関する。
電流を切り換えるまたは整流するために、IGBTまたはMOSFETなどのソリッドステート半導体スイッチを含むパワー半導体モジュールがさまざまなパワーエレクトロニクス用途で使用されている。重要かつ急成長している用途は、電気自動車またはハイブリッド電気自動車のためのコンバータシステムである。このような用途のための一般的なモジュールは、1200Vまでの電圧定格および数百アンペアの電流定格を有し得る。
本発明の目的は、製造が容易でありかつ組み立てが容易であるパワー半導体モジュールを提供すること、および/または、浮遊インダクタンスが低い電気的接続部を有するパワー半導体モジュールを提供することである。
パワー半導体モジュールは、基板および端子設計に関してより自由であるために、電気的性能を向上させることができる。トランスファー成形アプローチと組み合わせてリードフレームによって課される要件によって端子位置が制限されることはない。たとえば、DCリンクキャパシタへの接続部をより短くすることができる。なぜなら、端子溶接のためのバスバーの空間が不要であるからである。接続部がより短くなることにより、転流ループインダクタンスを低くすることができる。さらに、補助接続部を短くすることにより、ゲートインダクタンスを小さくすることができる。
図1は、パワー半導体チップ14が接着された基板12を備えるパワー半導体モジュール10を示す。なお、上記のように、たとえば2つ以上のパワー半導体チップ14が基板に接着されてもよい。しかし、図1にはパワー半導体チップ14が1つだけ示されている。
10 パワー半導体モジュール
12 基板
14 半導体チップ
16 セラミック層
18 上部金属化層
20 下部金属化層
21 ボンドワイヤ
22 冷却プレート
24 フィンまたはリブ
26 成形封止部
28 基板の境界
30 冷却プレートの境界
32 中央部
34 境界部
36 窓
38 補助端子領域
40 パワー端子領域
42 冷却体
43 冷却空洞
44 パワー半導体モジュールアセンブリ
46 パワー電気素子
48 補助端子
50 第1の端部
52 第2の端部
54 導電性ストリップ、パワー端子
56 中間部
58 第1の端部
60 第2の端部
62 鋳造材料
64 回路基板
66 ボンドワイヤ
68 ばね要素
70 共面端子構造
72 端子領域の列
74 導電性ストリップ
76 足部
Claims (14)
- パワー半導体モジュール(10)であって、
金属化層(18)を有する基板(12)と、
前記基板(12)に接着された少なくとも1つのパワー半導体チップ(14)と、
前記半導体チップ(14)および前記基板(12)を部分的に封止する成形封止部(26)とを備え、前記成形封止部(26)は、前記金属化層(18)の端子領域(38,40)を露出させる少なくとも1つの窓(36)を備え、前記パワー半導体モジュール(10)はさらに、
端部(58)が前記端子領域(40)に接着されたパワー端子(54)を備え、
前記成形封止部(26)は、前記半導体チップ(14)を封止する中央部(32)を備え、
前記窓(36)と前記基板(12)の境界(28)との間の前記成形封止部(26)の境界部(34)は、前記成形封止部(26)の前記中央部(32)の基板(12)上方最大高さよりも小さな基板(12)上方高さを有し、
前記パワー端子(54)の一部(56)は、前記基板(12)に平行な方向に前記境界部(34)の上方に突き出ていることにより、前記一部(56)の基板(12)上方垂直高さは、前記成形封止部(26)の前記中央部(32)の前記最大高さよりも小さい、パワー半導体モジュール(10)。 - 前記境界部(34)の前記基板(12)上方高さは、導体(21)の基板(12)上方最大高さよりも小さく、前記導体(21)は、前記成形封止部(26)において封止され、前記半導体チップ(14)および前記金属化層(18)に接着される、請求項1に記載のパワー半導体モジュール(10)。
- 前記境界部(34)は、前記基板(12)の前記境界(28)と重なり合う、請求項1または2に記載のパワー半導体モジュール(10)。
- 前記成形封止部(26)は、少なくとも2つの窓(36)を備え、各窓(36)は、前記金属化層の端子領域(38,40)を露出させ、
前記端子領域(38)のうちの少なくとも1つは、パワー端子領域であり、
前記端子領域(40)のうちの少なくとも1つは、補助端子領域である、先行する請求項のいずれか1項に記載のパワー半導体モジュール(10)。 - 前記境界部(34)は、少なくとも2つの窓(36)を提供する、先行する請求項のいずれか1項に記載のパワー半導体モジュール(10)。
- 2つの共面導体ストリップ(74)を有する2つのパワー端子(54)をさらに備え、
各パワー端子(54)は、それぞれの前記導体ストリップ(74)から突き出る少なくとも2つの足部(76)を、一方の前記パワー端子(54)からの足部(76)が他方の前記パワー端子(54)からの足部(76)と交互になるように備え、
前記パワー端子(54)からの前記足部(76)は、端子領域(40)の列(72)に接着され、前記端子領域(40)の各々は、前記成形封止部(26)の専用の窓(36)によって設けられる、先行する請求項のいずれか1項に記載のパワー半導体モジュール(10)。 - 第1の端部(50)が前記成形封止部(26)の窓(36)における端子領域(38)に接着され、第2の端部(52)が前記中央部(32)の上方に突き出ている補助端子(48)をさらに備える、先行する請求項のいずれか1項に記載のパワー半導体モジュール(10)。
- 前記成形封止部(26)の前記中央部(32)に取り付けられた回路基板(64)と、
窓(36)における端子領域(38)に接着され、前記回路基板(64)に接着されたボンドワイヤ(66)、および、前記印刷回路基板(64)に接続され、窓(36)における端子領域(38)に押し付けられた導電性ばね要素(68)のうちの少なくとも1つとをさらに備える、先行する請求項のいずれか1項に記載のパワー半導体モジュール(10)。 - 前記成形封止部(34)の窓(36)における端子領域(38,40)に接着された端子(48,54)の端部(50,58)は、前記窓(36)に充填された鋳造材料(62)に埋設される、先行する請求項のいずれか1項に記載のパワー半導体モジュール(10)。
- 前記パワー半導体チップ(14)に対向して前記基板(12)に取り付けられた冷却プレート(22)をさらに備え、
前記成形封止部(26)は、前記冷却プレート(22)の一方の側のみに設けられ、
前記成形封止部(26)の前記境界部(34)は、前記基板(12)の前記境界(28)の上方に延在しており、前記冷却プレート(22)上に配設される、先行する請求項のいずれか1項に記載のパワー半導体モジュール(10)。 - 冷却空洞(43)を有する冷却体(42)をさらに備え、前記冷却空洞(43)は、前記冷却体(42)に挿入された前記冷却プレート(22)によって閉じられ、
前記冷却プレート(22)は、前記冷却プレート(22)の境界(30)に沿って前記冷却体(42)に溶接される、請求項10に記載のパワー半導体モジュール(10)。 - パワー半導体モジュールアセンブリ(44)であって、
先行する請求項のいずれか1項に記載のパワー半導体モジュール(10)と、
パワー電気素子(46)とを備え、
前記パワー端子(54)は、前記パワー電気素子(46)と前記パワー半導体モジュール(10)とを直接相互接続する、パワー半導体モジュールアセンブリ(44)。 - パワー半導体モジュール(10)の製造方法であって、
金属化層(18)を有する基板(12)を設けるステップを備え、前記基板(12)には少なくとも1つのパワー半導体チップ(14)が接着され、前記方法はさらに、
前記半導体チップ(14)および前記基板(12)を成形封止部(26)に成形するステップを備え、前記成形封止部(26)は、前記半導体チップ(14)を封止する中央部(32)を備え、前記成形封止部(26)は、前記金属化層(18)の端子領域(38,40)を露出させる少なくとも1つの窓(36)を備え、前記窓(36)と前記基板(12)の境界(28)との間の前記成形封止部の境界部(34)は、前記成形封止部(26)の前記中央部(32)の最大高さよりも小さな基板(12)上方高さを有し、前記方法はさらに、
パワー端子(54)の端部(58)を前記端子領域(40)に接着するステップを備え、
前記パワー端子(56)の一部(56)は、前記基板(12)に平行な方向に前記境界部(34)の上方に突き出ていることにより、前記一部(56)の基板(12)上方垂直高さは、前記成形封止部(26)の前記中央部(32)の前記最大高さよりも小さい、方法。 - 前記基板(12)に取り付けられた冷却プレート(22)を冷却体(42)に溶接するステップと、
補助端子(48)を前記成形封止部(26)の窓(36)に設けられた端子領域(38,40)に接着するステップと、
導体ストリップ(54)を前記成形封止部(26)の窓(36)に設けられた端子領域(40)およびパワー電気素子(46)に接着するステップとをさらに備える、請求項13に記載の方法。
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