JP2020512682A - イオン注入側壁を有するゲート・トレンチを備えるパワー半導体デバイス及び関連方法 - Google Patents
イオン注入側壁を有するゲート・トレンチを備えるパワー半導体デバイス及び関連方法 Download PDFInfo
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Abstract
Description
本発明は、協力協定番号W911NF−12−2−0064の下で陸軍研究所から資金提供された政府の助成を受けてなされたものである。政府は、本発明について一定の権利を有する。
上面と、p+シリコン・カーバイドの深部遮蔽パターン140との上にエピタキシャル成長よって形成される。この中濃度にドーピングされたp型シリコン・カーバイド層170は、デバイス100のPウェル172として機能する。高濃度にドーピングされたp+シリコン・カーバイド領域174は、Pウェル172内にイオン注入により形成され、その下の深部遮蔽パターン140に電気的に接続される。Pウェル172は、高濃度にドーピングされた領域174隣接する中濃度にドーピングされたp型領域176をさらに備える。p型領域174、176は、共にPウェル172を形成する。トランジスタ・チャネルは、後述するように、Pウェル172の中濃度にドーピングされた領域176内に形成され得る。基板110、ドリフト領域120(電流拡散層130を備える)、及び中濃度にドーピングされたp型層170は、その内部に形成される多様な領域/パターンと共に、MOSFET100の半導体層構造106を構成する。
Claims (39)
- ワイド・バンドギャップ半導体材料を含むドリフト領域を備える半導体層構造であって、前記ドリフト領域は第1の導電型を有する、半導体層構造と、
前記半導体層構造の上部内のゲート・トレンチであって、前記ゲート・トレンチは、前記半導体層構造の前記上部における第1方向に延在する第1及び第2の対向する側壁を有する、ゲート・トレンチと、
前記ゲート・トレンチの底面下方の前記半導体層構造内の前記第1の導電型と反対の第2導電型を有する深部遮蔽パターンと、
前記ゲート・トレンチの前記第1の側壁内に、前記第2の導電型を有する深部遮蔽接続と、
前記ゲート・トレンチの前記第2の側壁内に前記第1の導電型を有する半導体チャネル領域とを備える、半導体デバイス。 - 前記半導体チャネル領域が、前記深部遮蔽接続パターンの一部分を含む第1の側壁の一部分の正反対の前記第2の側壁の一部分である、請求項1に記載の半導体デバイス。
- 前記半導体層構造が、前記第2の導電型を有するウェル領域をさらに備え、前記深部遮蔽接続パターンが、前記深部遮蔽形態を前記ウェル領域に電気的に接続する、請求項2に記載の半導体デバイス。
- 前記ゲート・トレンチが、前記半導体デバイスの活性領域内に位置し、前記半導体デバイスは、前記活性領域を囲む終端領域をさらに備え、前記終端領域は、前記半導体層構造の前記上部に複数の終端トレンチを備える、請求項1から3までのいずれか一項に記載の半導体デバイス。
- 前記それぞれの終端トレンチ下方に設けられる前記第2の導電型を有する複数の終端構造を更に備える、請求項4に記載の半導体デバイス。
- 前記終端構造がまた、前記それぞれの終端トレンチの第1の部分の外側側壁ではなく、内側側壁内へ、且つ前記それぞれの終端トレンチの第2の部分の内側側壁でなく、外側側壁内へと延在する、請求項4から5のいずれか一項に記載の半導体デバイス。
- 前記深部遮蔽パターンの底部が、各終端構造の底部として前記半導体層構造内でほぼ同一の深さである、請求項4から6までのいずれか一項に記載の半導体デバイス。
- 前記終端構造が、ガード・リングを備える、請求項4から7までのいずれか一項に記載の半導体デバイス。
- 前記ゲート・トレンチの前記底面並びに前記第1及び第2の側壁を少なくとも部分的に被覆する、前記ゲート・トレンチ内のゲート絶縁層と、
前記ゲート絶縁層上の前記ゲート・トレンチ内のゲート電極と、
前記半導体層構造の前記上部上の第1のソース/ドレイン・コンタクトと、
前記半導体層構造の下面上の第2のソース/ドレイン・コンタクトとをさらに備える、請求項1から8までのいずれか一項に記載の半導体デバイス。 - 前記半導体層構造の前記上部内の追加の複数のゲート・トレンチであって、前記追加の複数のゲート・トレンチの各々は、前記第1の方向に延在するそれぞれの第1及び第2の対向する側壁を有する、追加の複数のゲート・トレンチと、
前記それぞれの追加の複数のゲート・トレンチの底面下方の前記半導体層構造内の前記第2の導電型を有する追加の複数の深部遮蔽パターンと、
前記それぞれの追加の複数のゲート・トレンチの第1の側壁内の前記第2の導電型を有する追加の複数の深部遮蔽接続パターンと、
前記それぞれの追加の複数のゲート・トレンチの前記第2の側壁内の前記第1の導電型を有する追加の複数の半導体チャネル領域とをさらに備える、請求項1から9までのいずれか一項に記載の半導体デバイス。 - 前記ゲート・トレンチの前記第1の側壁が、前記半導体層構造の前記上部に関して80度より小さい角度で傾けられる、請求項1から10までのいずれか一項に記載の半導体デバイス。
- 前記深部遮蔽パターンが、前記ゲート・トレンチの下方の複数の間隔を空けられた深部遮蔽領域を備え、前記深部遮蔽接続パターンが、前記ゲート・トレンチの前記第1の側壁内の複数の間隔を空けられた深部遮蔽接続を備え、前記半導体チャネル領域が、第1及び第2の前記深部遮蔽接続領域間にある前記第1の側壁の一部分の反対側の前記第2の側壁の一部分である、請求項1から11までのいずれか一項に記載の半導体デバイス。
- 前記深部遮蔽パターンが、前記ゲート・トレンチ下方で延在する連続した深部遮蔽領域を含み、前記深部遮蔽接続パターンが、前記ゲート・トレンチの前記第1の側壁内の連続した深部遮蔽接続領域を含む、請求項1から12までのいずれか一項に記載の半導体デバイス。
- 前記ワイド・バンドギャップ半導体が、シリコン・カーバイドを含む、請求項1から13までのいずれか一項に記載の半導体デバイス。
- 活性領域及び終端領域を有する半導体層構造であって、第1の導電型を有するワイド・バンドギャップ半導体材料を含むドリフト領域を備える、半導体層構造と、
前記半導体層構造の上部内に形成された前記活性領域内の複数のゲート・トレンチであって、第1の方向に延在し、前記第1の方向と垂直な第2の方向で互いから間隔を空けられている、複数のゲート・トレンチと、
前記第1の導電型と反対の第2の導電型を有するドーパントでドーピングされた複数の深部遮蔽パターンであって、それぞれのゲート・トレンチ下方の前記半導体層構造内に配置される、複数の深部遮蔽パターンと、
前記半導体層構造の前記上部内に形成された前記終端領域内の複数の終端トレンチと、
前記第2の導電型を有するドーパントでドーピングされた複数の終端構造であって、前記それぞれの終端トレンチの下方の前記半導体層構造内に配置される、終端構造とを備える、半導体デバイス。 - 各終端構造がさらに、前記それぞれの終端トレンチの少なくとも1つの側壁内に延在する、請求項15に記載の半導体デバイス。
- 前記それぞれのゲート・トレンチの第1の側壁内で前記第2の導電型を有する複数の深部遮蔽接続パターンをさらに備え、各深部遮蔽接続パターンが、複数の前記深部遮蔽パターンのうちのそれぞれの1つを共通のソース・コンタクトに電気的に接続する、請求項15又は16に記載の半導体デバイス。
- 前記それぞれのゲート・トレンチの前記第2の側壁内の前記第1の導電型を有する複数の半導体チャネル領域をさらに備える、請求項15から17までのいずれか一項に記載の半導体デバイス。
- 各半導体チャネル領域が、複数の前記深部遮蔽接続パターンのうちのそれぞれの1つの一部分を含む前記第1の側壁の正反対の部分である、請求項15から18までのいずれか一項に記載の半導体デバイス。
- 前記終端構造がまた、前記それぞれの終端トレンチの第1の部分の外側側壁ではなく、内側側壁内へ、且つ前記それぞれの終端トレンチの第2の部分の内側側壁でなく、外側側壁内へと延在する、請求項15から19までのいずれか一項に記載の半導体デバイス。
- 各深部遮蔽パターンの底部が、各終端構造の底部として前記半導体層構造内でほぼ同一の深さである、請求項15から20までのいずれか一項に記載の半導体デバイス。
- 前記ワイド・バンドギャップ半導体が、シリコン・カーバイドを含む、請求項15から21までのいずれか一項に記載の半導体デバイス。
- ワイド・バンドギャップ半導体層構造を基板上に形成するステップであって、前記半導体層構造は、第1の導電型を有するドリフト領域を備える、ステップと、
複数のゲート・トレンチを前記半導体層構造の上部内に形成するステップであって、前記ゲート・トレンチは、第1の方向に延在し、前記第1の方向と垂直な第2の方向で互いから間隔を空けられており、各ゲート・トレンチは、底面と、前記第1の方向に延在する第1の側壁と、前記第1の方向に延在する第2の側壁とを備える、ステップと、
前記第1の導電型と反対の前記第2の導電型を有するドーパントを前記ゲート・トレンチの前記底面及び前記第1の側壁内に注入するステップとを含む、半導体デバイス形成方法。 - 前記第2の導電型を有する前記ドーパントが、角度設定イオン注入を用いて前記ゲート・トレンチの前記第1の側壁内に注入される、請求項23に記載の方法。
- 前記半導体デバイスが、前記半導体層構造の第1の主面上の第1のソース/ドレイン・コンタクトと、前記第1の主面と反対の前記半導体層構造の第2の主面上の第2のソース/ドレイン・コンタクトとを備える垂直方向の半導体デバイスである、請求項23又は24に記載の方法。
- 前記半導体層構造が、前記ゲート・トレンチ間に前記第2の導電型を有する複数のウェル領域を備える、請求項23から25までのいずれか一項に記載の方法。
- 前記ゲート・トレンチの前記底面内に注入される前記第2の導電型ドーパントが、前記それぞれのゲート・トレンチ下方の複数の深部遮蔽パターンを形成し、前記ゲート・トレンチの前記第1の側壁内に注入される前記第2の導電型ドーパントが、前記深部遮蔽領域を前記それぞれのウェル領域に電気的に接続する複数の深部遮蔽接続パターンを形成する、請求項23から26までのいずれか一項に記載の方法。
- チャネル領域が、前記ゲート・トレンチの前記それぞれの第2の側壁内に形成される、請求項23から27までのいずれか一項に記載の方法。
- 各チャネル領域が、複数の前記深部遮蔽接続パターンのうちのそれぞれの1つの一部分の正反対である、請求項23から28までのいずれか一項に記載の方法。
- 前記ウェル領域が、前記半導体層構造であり、前記半導体層構造は、単一のエピタキシャル成長工程で形成される、請求項23から29までのいずれか一項に記載の方法。
- 前記ゲート・トレンチの前記第1の側壁が、前記半導体層構造の上部に関して80度より小さい角度で傾けられる、請求項23から30までのいずれか一項に記載の方法。
- 前記半導体デバイスの終端領域内に終端構造を形成するステップをさらに含み、前記終端構造が、前記深部遮蔽パターン及び前記深部遮蔽接続パターンと同時にイオン注入よって形成される、請求項23から31までのいずれか一項に記載の方法。
- 前記終端構造を形成するステップが、
前記終端領域内に複数の終端トレンチを形成するステップと、
前記第2の導電型を有するドーパントを用いて各終端トレンチの底面及び第1の側壁に注入するステップとを含む、請求項23から32までのいずれか一項に記載の方法。 - 前記終端トレンチの前記底面及び第1の側壁が、角度設定イオン注入により形成される、請求項23から33までのいずれか一項に記載の方法。
- 前記ゲート・トレンチの前記第2の側壁内に第2の導電型ドーパントを注入するために、第2の角度設定イオン注入を形成するステップをさらに含む、請求項23から34までのいずれか一項に記載の方法。
- 各深部遮蔽パターンが、各ゲート・トレンチ下方に複数の間隔を空けられた深部遮蔽領域を備える、請求項23から35までのいずれか一項に記載の方法。
- 前記ワイド・バンドギャップ半導体が、シリコン・カーバイドを含む、請求項23から36までのいずれか一項に記載の方法。
- 前記角度設定イオン注入の少なくとも一部分が、垂直方向注入から2から15度の間の注入角度にある、請求項23から37までのいずれか一項に記載の方法。
- 前記角度設定イオン注入が、ドーパントを2つ以上の角度で、且つ2つ以上の注入エネルギーで注入する、請求項23から38までのいずれか一項に記載の方法。
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JP7309840B2 (ja) | 2023-07-18 |
EP3552230A1 (en) | 2019-10-16 |
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