JP2020155631A5 - - Google Patents
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- Publication number
- JP2020155631A5 JP2020155631A5 JP2019053623A JP2019053623A JP2020155631A5 JP 2020155631 A5 JP2020155631 A5 JP 2020155631A5 JP 2019053623 A JP2019053623 A JP 2019053623A JP 2019053623 A JP2019053623 A JP 2019053623A JP 2020155631 A5 JP2020155631 A5 JP 2020155631A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal layer
- wiring
- pad
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims 4
- 238000009713 electroplating Methods 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 239000007769 metal material Substances 0.000 claims 1
- 238000009751 slip forming Methods 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019053623A JP7253946B2 (ja) | 2019-03-20 | 2019-03-20 | 配線基板及びその製造方法、半導体パッケージ |
| US16/811,731 US11171081B2 (en) | 2019-03-20 | 2020-03-06 | Wiring substrate, semiconductor package and method of manufacturing wiring substrate |
| US17/497,158 US11594478B2 (en) | 2019-03-20 | 2021-10-08 | Wiring substrate, semiconductor package and method of manufacturing wiring substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019053623A JP7253946B2 (ja) | 2019-03-20 | 2019-03-20 | 配線基板及びその製造方法、半導体パッケージ |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2020155631A JP2020155631A (ja) | 2020-09-24 |
| JP2020155631A5 true JP2020155631A5 (enExample) | 2021-12-23 |
| JP7253946B2 JP7253946B2 (ja) | 2023-04-07 |
Family
ID=72513706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019053623A Active JP7253946B2 (ja) | 2019-03-20 | 2019-03-20 | 配線基板及びその製造方法、半導体パッケージ |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US11171081B2 (enExample) |
| JP (1) | JP7253946B2 (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11380609B2 (en) * | 2018-05-21 | 2022-07-05 | Intel Corporation | Microelectronic assemblies having conductive structures with different thicknesses on a core substrate |
| JP2021177515A (ja) * | 2020-05-07 | 2021-11-11 | 富士通株式会社 | 基板ユニット |
| JP2022070723A (ja) * | 2020-10-27 | 2022-05-13 | 味の素株式会社 | プリント配線板及びその製造方法 |
| CN114695126A (zh) * | 2020-12-30 | 2022-07-01 | 江苏中科智芯集成科技有限公司 | 一种半导体芯片封装方法及封装结构 |
| US12484157B2 (en) * | 2021-03-18 | 2025-11-25 | Panasonic Intellectual Property Management Co., Ltd. | Adhesive for provisionally fixing electronic component to solder precoat and method for producing electronic component mounted substrate |
| JP7622605B2 (ja) * | 2021-10-13 | 2025-01-28 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
| US20240178155A1 (en) * | 2022-11-30 | 2024-05-30 | Texas Instruments Incorporated | Multilevel package substrate with box shield |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005311245A (ja) | 2004-04-26 | 2005-11-04 | Fujikura Ltd | ビアホール形成方法 |
| TWI495051B (zh) * | 2011-07-08 | 2015-08-01 | 欣興電子股份有限公司 | 無核心層之封裝基板及其製法 |
| US9691686B2 (en) * | 2014-05-28 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact pad for semiconductor device |
| JP6530298B2 (ja) | 2015-10-09 | 2019-06-12 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
| TWI590350B (zh) * | 2016-06-30 | 2017-07-01 | 欣興電子股份有限公司 | 線路重分佈結構的製造方法與線路重分佈結構單元 |
| US10043740B2 (en) * | 2016-07-12 | 2018-08-07 | Intel Coporation | Package with passivated interconnects |
| KR20190088465A (ko) * | 2016-11-28 | 2019-07-26 | 미쓰이금속광업주식회사 | 다층 배선판의 제조 방법 |
| JP7208011B2 (ja) * | 2016-11-28 | 2023-01-18 | 三井金属鉱業株式会社 | 多層配線板の製造方法 |
| JP6924084B2 (ja) * | 2017-06-26 | 2021-08-25 | 新光電気工業株式会社 | 配線基板 |
| US10535590B2 (en) * | 2017-12-29 | 2020-01-14 | Intel Corporation | Multi-layer solder resists for semiconductor device package surfaces and methods of assembling same |
| EP3732710A4 (en) * | 2017-12-30 | 2021-11-17 | INTEL Corporation | GALVANIC CORROSION PROTECTION FOR SEMI-CONDUCTOR HOUSING |
| US20200075468A1 (en) * | 2018-09-04 | 2020-03-05 | International Business Machines Corporation | Dedicated Integrated Circuit Chip Carrier Plane Connected to Decoupling Capacitor(s) |
| US11302619B2 (en) * | 2019-10-01 | 2022-04-12 | Advanced Semiconductor Engineering, Inc. | Device structure and method for manufacturing the same |
-
2019
- 2019-03-20 JP JP2019053623A patent/JP7253946B2/ja active Active
-
2020
- 2020-03-06 US US16/811,731 patent/US11171081B2/en active Active
-
2021
- 2021-10-08 US US17/497,158 patent/US11594478B2/en active Active
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