JP7253946B2 - 配線基板及びその製造方法、半導体パッケージ - Google Patents

配線基板及びその製造方法、半導体パッケージ Download PDF

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Publication number
JP7253946B2
JP7253946B2 JP2019053623A JP2019053623A JP7253946B2 JP 7253946 B2 JP7253946 B2 JP 7253946B2 JP 2019053623 A JP2019053623 A JP 2019053623A JP 2019053623 A JP2019053623 A JP 2019053623A JP 7253946 B2 JP7253946 B2 JP 7253946B2
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layer
wiring
metal layer
insulating layer
pad
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JP2020155631A (ja
JP2020155631A5 (enExample
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智晃 町田
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2019053623A priority Critical patent/JP7253946B2/ja
Priority to US16/811,731 priority patent/US11171081B2/en
Publication of JP2020155631A publication Critical patent/JP2020155631A/ja
Priority to US17/497,158 priority patent/US11594478B2/en
Publication of JP2020155631A5 publication Critical patent/JP2020155631A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
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    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/49894—Materials of the insulating layers or coatings
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
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JP2019053623A JP7253946B2 (ja) 2019-03-20 2019-03-20 配線基板及びその製造方法、半導体パッケージ
US16/811,731 US11171081B2 (en) 2019-03-20 2020-03-06 Wiring substrate, semiconductor package and method of manufacturing wiring substrate
US17/497,158 US11594478B2 (en) 2019-03-20 2021-10-08 Wiring substrate, semiconductor package and method of manufacturing wiring substrate

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JP2019053623A JP7253946B2 (ja) 2019-03-20 2019-03-20 配線基板及びその製造方法、半導体パッケージ

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US11380609B2 (en) * 2018-05-21 2022-07-05 Intel Corporation Microelectronic assemblies having conductive structures with different thicknesses on a core substrate
JP2021177515A (ja) * 2020-05-07 2021-11-11 富士通株式会社 基板ユニット
JP2022070723A (ja) * 2020-10-27 2022-05-13 味の素株式会社 プリント配線板及びその製造方法
CN114695126A (zh) * 2020-12-30 2022-07-01 江苏中科智芯集成科技有限公司 一种半导体芯片封装方法及封装结构
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