JP6924084B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
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- JP6924084B2 JP6924084B2 JP2017124580A JP2017124580A JP6924084B2 JP 6924084 B2 JP6924084 B2 JP 6924084B2 JP 2017124580 A JP2017124580 A JP 2017124580A JP 2017124580 A JP2017124580 A JP 2017124580A JP 6924084 B2 JP6924084 B2 JP 6924084B2
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Description
以下、第1実施形態を説明する。
図1(a)に示すように、半導体装置1は、配線基板10と、配線基板10に実装された半導体素子51を含む。
図1(b)に示すように、配線基板10は、配線層11と、絶縁層12と、磁性層13と、配線層14と、絶縁層15と、配線層16と、絶縁層17と、配線層18とを含み、これらが積層された構造を有している。配線層14は、コイル41のコイル配線14Pを含む。
上記の配線基板10の製造工程を説明する。
図2(a)に示すように、支持基板60を準備する。支持基板60は、例えば、キャリア付金属箔を用いることができる。なお、支持基板60として、公知の他の支持基板を用いることもできる。支持基板60は、キャリア板61と、キャリア板61の一方の面(図2(a)では上面)に剥離層(図示略)を介して積層された極薄の金属箔62とを有している。キャリア板61の材料としては、例えば、CuやCu合金を用いることができる。金属箔62の材料としては、例えば、CuやCu合金を用いることができる。
本実施形態の配線基板10は、磁性層13の上面13aのコイル配線14Pを有している。つまり、磁性層13は、コイル配線14Pの下面に接している。コイル配線14Pは、平面視において渦状に形成されている。
図7(a)に示す第1のモデル70aは、配線層71、絶縁層81、配線層72、絶縁層82、配線層73、絶縁層83、配線層74、絶縁層84、配線層75、絶縁層85、配線層76、絶縁層86、配線層77、絶縁層87、配線層78がこの順番で積層された配線基板である。配線層71の外部接続用パッド71Pの下面には、外部接続端子91が接続されている。配線層72〜77は、絶縁層81〜86を貫通して配線層72〜77を配線層71〜76にそれぞれ接続するビア配線を含む。この第1のモデル70aは、磁性層が設けられていない。
(1−1)半導体装置1は、配線基板10と、配線基板10に実装された半導体素子51を含む。配線基板10は、配線層11と、絶縁層12と、磁性層13と、配線層14と、絶縁層15と、配線層16と、絶縁層17と、配線層18とを含み、これらが積層された構造を有している。配線層14は、磁性層13の上面13aに形成されている。配線層14は、磁性層13の上面のコイル配線14Pを有している。コイル配線14Pは、磁性層13の上面13aにおいて、例えば、渦状(スパイラル状)に形成されたコイル(平面コイル)である。配線層11の配線部11Aと、配線層16と、配線層18とは、配線基板10において信号を伝達する経路(信号配線構造)である。磁性層13は、第2絶縁層15Bを貫通する開口部15Xの内部のビア配線16Vに対して非接触である。つまり、本実施形態において、配線基板10の磁性層13は、配線基板10の信号配線構造に直接接していない。このような配線基板10では、磁性層13による信号の伝達特性の向上、挿入損失を低減できる。
以下、第2実施形態を説明する。
なお、この実施形態において、上記実施形態と同じ構成部材については同じ符号を付し、その説明の一部又は全てを省略する場合がある。
半導体素子51は、外部接続端子52を介して、配線基板110の外部接続用パッドP21に接続されている。半導体素子51は、この外部接続用パッドP21により、配線基板110に対してフリップチップ接続されている。半導体素子51は、CPU(Central Processing Unit)やGPU(Graphics Processing Unit)等のロジックチップ、DRAM(Dynamic Random Access Memory)やSRAM(Static Random Access Memory)等のメモリチップ、等である。外部接続端子52は、例えば、はんだバンプや金バンプである。はんだバンプの材料としては、例えば、鉛を含む合金、錫と金との合金、錫と銅との合金、錫と銀との合金、錫と銀と銅の合金などを用いることができる。
図9(b)に示すように、配線基板110は、配線層111と、磁性層113と、配線層114と、絶縁層115と、配線層116と、絶縁層117と、配線層118とを含み、これらが積層された構造を有している。配線層114は、上述のコイル141のコイル配線114Pを含む。
次に、本実施形態の配線基板110の製造工程を説明する。
図10(a)に示すように、支持基板60を準備する。支持基板60は、例えば、キャリア付金属箔を用いることができる。なお、支持基板60として、公知の他の支持基板を用いることもできる。支持基板60は、キャリア板61と、キャリア板61の一方の面(図2(a)では上面)に剥離層(図示略)を介して積層された極薄の金属箔62とを有している。キャリア板61の材料としては、例えば、CuやCu合金を用いることができる。金属箔62の材料としては、例えば、CuやCu合金を用いることができる。
(2−1)上記の第1実施形態の配線基板10と同様の効果を奏する。
(2−2)上記の第1実施形態の絶縁層12が省略されている。このため、第1実施形態と比べ、配線基板110を薄くできる。
以下、第3実施形態を説明する。
なお、この実施形態において、上記実施形態と同じ構成部材については同じ符号を付し、その説明の一部又は全てを省略する場合がある。
半導体素子251は、外部接続端子252A,252Bを介して、配線基板210の外部接続用パッドP31A,P31Bに接続されている。半導体素子251は、この外部接続用パッドP31A,P31Bにより、配線基板210に対してフリップチップ接続されている。半導体素子251は、CPU(Central Processing Unit)やGPU(Graphics Processing Unit)等のロジックチップ、等である。外部接続端子252A,252Bは、例えば、はんだバンプや金バンプである。はんだバンプの材料としては、例えば、鉛を含む合金、錫と金との合金、錫と銅との合金、錫と銀との合金、錫と銀と銅の合金などを用いることができる。
次に、本実施形態の配線基板210の製造工程を説明する。
図16(a)に示すように、コア基板211を用意する。コア基板211は、例えば、銅張積層板(Copper Clad Laminate:CCL)を用いることができる。このコア基板211に貫通孔211X,211Yを形成し、電解めっきや導電性ペースト充填等の方法によって貫通孔211X,211Yの内部に貫通電極212A,212Bを形成する。その後、サブトラクティブ法によって配線層221(221A,221P),231(231A,231B)を形成する。
(3−1)コア基板211を含む配線基板210において、上述の第1実施形態の配線基板10と同様の効果を奏する。
以下、第4実施形態を説明する。
なお、この実施形態において、上記実施形態と同じ構成部材については同じ符号を付し、その説明の一部又は全てを省略する場合がある。
半導体素子251は、外部接続端子252A,252Bを介して、配線基板310の外部接続用パッドP41A,P41Bに接続されている。半導体素子251は、この外部接続用パッドP41A,P41Bにより、配線基板310に対してフリップチップ接続されている。半導体素子251は、CPU(Central Processing Unit)やGPU(Graphics Processing Unit)等のロジックチップ、等である。外部接続端子252A,252Bは、例えば、はんだバンプや金バンプである。はんだバンプの材料としては、例えば、鉛を含む合金、錫と金との合金、錫と銅との合金、錫と銀との合金、錫と銀と銅の合金などを用いることができる。
次に、本実施形態の配線基板310の製造工程を説明する。
図20(a)に示す工程では、コア基板311に、貫通電極312A,312B、配線層321,331を形成する。図20(2)に示すコア基板311を用意する。コア基板311は、例えば、銅張積層板(CCL)を用いることができる。このコア基板311に貫通孔311X,311Yを形成し、電解めっきや導電性ペースト充填等の方法によって貫通孔311X,311Yの内部に貫通電極312A,312Bを形成する。その後、サブトラクティブ法によって配線層321,331を形成する。配線層321は、配線部321Aとコイル配線321Pを含む。配線層331は、配線部331A,331Bを含む。
(4−1)コア基板311を含む配線基板310において、上記の第1実施形態の配線基板10と同様の効果を奏する。
以下、比較例を説明する。
なお、この比較例において、上記実施形態と同じ構成部材については同じ符号を付し、その説明の一部又は全てを省略する場合がある。
半導体素子251は、外部接続端子252A,252Bを介して、配線基板410の外部接続用パッドP41A,P41Bに接続されている。半導体素子251は、この外部接続用パッドP41A,P41Bにより、配線基板410に対してフリップチップ接続されている。半導体素子251は、CPU(Central Processing Unit)やGPU(Graphics Processing Unit)等のロジックチップ、等である。外部接続端子252A,252Bは、例えば、はんだバンプや金バンプである。はんだバンプの材料としては、例えば、鉛を含む合金、錫と金との合金、錫と銅との合金、錫と銀との合金、錫と銀と銅の合金などを用いることができる。
・上記第1実施形態では、図1(b)に示すように、配線層11(配線部11A,11B)の下面11Ab、11Bbが絶縁層12の下面12bより上方に位置して、配線層11(配線部11A,11B)の下面11Ab、11Bbと絶縁層12の下面12bの側の開口部12bX,12bYとによる凹部を形成した。これに対し、配線層11(配線部11A,11B)の下面11Ab、11Bbを、絶縁層12の下面12bと同じに位置するようにしてもよい。第2実施形態でも同様に、配線層111(配線部111A,111B)の下面を、磁性層113及び絶縁層115の下面と同じに位置するようにしてもよい。
例えば、図16(c)に示す工程において、磁性層222の開口部222Xと絶縁層232の開口部232Xとを形成したが、磁性層222の開口部222Xを形成した後に図17(a)に示す絶縁層223を形成する。その後、絶縁層232の開口部232Xを形成して図17(b)に示す配線層233を形成するようにしてもよい。
13 磁性層
14P コイル配線
51 半導体素子
Claims (8)
- 半導体素子が実装される配線基板であって、
第1のコイル配線と、
前記第1のコイル配線の下面と接し、厚さ方向に貫通する開口部を有する磁性層と、
前記第1のコイル配線と、前記磁性層の上面と、前記開口部の内壁面と、を覆う第1の絶縁層と、
前記第1の絶縁層の上面に形成され、前記第1のコイル配線に接続されて螺旋状のコイルを形成する第2のコイル配線と、
前記半導体素子の信号が前記磁性層の開口部の内部を通過するように形成され、前記第1の絶縁層の上面の第1の配線部と、前記磁性層の開口部の内部に設けられて前記第1の配線部に接続された第1のビア配線と、を有する信号配線構造と、を有し、
前記信号配線構造に対して前記磁性層は接していないこと、
を特徴とする配線基板。 - 前記磁性層の下面を覆う第2の絶縁層を有し、
前記信号配線構造は、下面を露出するように前記第2の絶縁層に埋設され、前記第1のビア配線に接続された第2の配線部を有すること、
を特徴とする請求項1に記載の配線基板。 - 下面を露出するように前記第2の絶縁層に埋設された第3の配線部と、
前記第3の配線部を前記第1のコイル配線に接続する第2のビア配線と、を有すること、
を特徴とする請求項2に記載の配線基板。 - 前記信号配線構造は、前記磁性層の開口部の内部であって下面が露出するように前記第1の絶縁層に埋設され、前記第1のビア配線に接続された第2の配線部を有すること、
を特徴とする請求項1に記載の配線基板。 - 下面が露出するように前記磁性層に埋設された第3の配線部と、
前記第3の配線部を前記第1のコイル配線に接続する第2のビア配線と、を有すること、
を特徴とする請求項4に記載の配線基板。 - 半導体素子が実装される配線基板であって、
上面と下面とを有する絶縁層と、
前記絶縁層の下面に形成された第1のコイル配線と、
前記絶縁層の上面に形成され、前記第1のコイル配線に接続されて螺旋状のコイルを形成する第2のコイル配線と、
前記絶縁層の下面と前記第1のコイル配線とを覆うように形成され、厚さ方向に貫通する開口部を有する磁性層と、
前記半導体素子の信号が前記磁性層の開口部の内部を通過するように形成された信号配線構造と、を有し、
前記信号配線構造に対して前記磁性層は接していないこと、
を特徴とする配線基板。 - 前記信号配線構造は、前記絶縁層の下面に形成された配線部を有し、
前記磁性層の開口部は、前記配線部と、前記絶縁層の下面のうちの前記配線部の周囲とを露出するように形成されていること、
を特徴とする請求項6に記載の配線基板。 - 前記磁性層の下面と前記開口部の内壁面と前記配線部の周囲の前記絶縁層の下面と前記配線部の一部とを覆い、前記配線部の下面の一部を露出する開口部を有する第2の絶縁層を含むこと、
を特徴とする請求項7に記載の配線基板。
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