JP2020102592A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2020102592A JP2020102592A JP2018241523A JP2018241523A JP2020102592A JP 2020102592 A JP2020102592 A JP 2020102592A JP 2018241523 A JP2018241523 A JP 2018241523A JP 2018241523 A JP2018241523 A JP 2018241523A JP 2020102592 A JP2020102592 A JP 2020102592A
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- insulating film
- interlayer insulating
- gate electrode
- semiconductor substrate
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Abstract
Description
14 :トレンチ
16 :ポリシリコン層
16a :凹部
18 :ゲート電極
18a :凹部
20 :層間絶縁膜
20a :凹部
22 :レジスト
24 :上部電極
Claims (1)
- 半導体装置の製造方法であって、
表面にトレンチを有する半導体基板の前記トレンチ内にゲート電極を形成する工程であって、前記ゲート電極の表面に凹部が形成されるように前記ゲート電極を形成する工程と、
前記ゲート電極の前記表面と前記半導体基板の前記表面を覆う層間絶縁膜を形成する工程であって、前記ゲート電極の前記凹部に沿って前記層間絶縁膜の表面に凹部が形成されるように前記層間絶縁膜を形成する工程と、
調整層を前記層間絶縁膜の前記凹部内に形成する工程であって、前記ゲート電極の上部の前記調整層の厚みが前記半導体基板の前記表面の上部の前記調整層の厚みよりも厚くなるように前記調整層を形成する工程と、
前記調整層に対するエッチングレートが前記層間絶縁膜に対するエッチングレートよりも遅い条件で前記調整層と前記層間絶縁膜をエッチングすることによって、前記調整層を除去し、前記半導体基板の前記表面を覆う部分の前記層間絶縁膜の少なくとも一部を除去して前記半導体基板の前記表面を露出させ、前記ゲート電極の上部に前記層間絶縁膜を残存させる工程、
を有する製造方法。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58102539A (ja) * | 1981-12-14 | 1983-06-18 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2006173289A (ja) * | 2004-12-15 | 2006-06-29 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法 |
JP2008294198A (ja) * | 2007-05-24 | 2008-12-04 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法 |
US20100187602A1 (en) * | 2009-01-29 | 2010-07-29 | Woolsey Debra S | Methods for making semiconductor devices using nitride consumption locos oxidation |
JP2012174989A (ja) * | 2011-02-23 | 2012-09-10 | Toshiba Corp | 半導体装置の製造方法 |
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2018
- 2018-12-25 JP JP2018241523A patent/JP7070392B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58102539A (ja) * | 1981-12-14 | 1983-06-18 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2006173289A (ja) * | 2004-12-15 | 2006-06-29 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法 |
JP2008294198A (ja) * | 2007-05-24 | 2008-12-04 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法 |
US20100187602A1 (en) * | 2009-01-29 | 2010-07-29 | Woolsey Debra S | Methods for making semiconductor devices using nitride consumption locos oxidation |
JP2012174989A (ja) * | 2011-02-23 | 2012-09-10 | Toshiba Corp | 半導体装置の製造方法 |
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