JP2020071893A - 記憶回路 - Google Patents
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- JP2020071893A JP2020071893A JP2018206352A JP2018206352A JP2020071893A JP 2020071893 A JP2020071893 A JP 2020071893A JP 2018206352 A JP2018206352 A JP 2018206352A JP 2018206352 A JP2018206352 A JP 2018206352A JP 2020071893 A JP2020071893 A JP 2020071893A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1677—Verifying circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1697—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0097—Erasing, e.g. resetting, circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0073—Write using bi-directional cell biasing
Abstract
Description
さらに本発明は、電源投入時の起動時間を短縮させることが可能な記憶回路を提供することを目的とする。
前記ノードに保持されたデータが第2の論理レベルであるとき、前記可変抵抗素子のリセット書込みを行う。ある実施態様では、前記不揮発性記憶回路は、前記ノードとソース線との間に直列に接続されたアクセス用トランジスタと可変抵抗素子とを含み、前記可変抵抗素子のセット書込みを行うとき、アクセス用トランジスタを導通状態にし、前記ノードからソース線へ向かうバイアスを前記可変抵抗素子に印加し、前記可変抵抗素子のリセット書込みを行うとき、アクセス用トランジスタを導通状態にし、前記ソース線から前記ノードに向かうバイアスを前記可変抵抗素子に印加する。ある実施態様では、前記不揮発性記憶回路の記憶されたデータを前記ノードに設定するとき、セット書込みを行った可変抵抗素子に対してリセット書込みを行い、リセット書込みを行った可変抵抗素子に対してセット書込みを行う。ある実施態様では、前記ノードは、トランジスタを介してビット線に接続され、前記可変抵抗素子に記憶されたデータを前記ビット線を介して読み出すことによりベリファイする。ある実施態様では、記憶回路はさらに、他のノードに接続された他の不揮発性記憶回路を含み、当該他の不揮発性記憶回路は、電源投入時に必要とされるブートデータを記憶する。ある実施態様では、電源投入時、前記他の不揮発性記憶回路に記憶されたブートデータが第1のノードに読み出される。ある実施態様では、前記他の不揮発性記憶回路は、前記他のノードとソース線との間に直列に接続されたアクセス用トランジスタと可変抵抗素子とを含む。
V1、V2:電圧供給部
TP1、TP2:P型トランジスタ
TN1〜TN4、Q1、Q2:N型トランジスタ
NV1、NV2:不揮発性記憶回路
VR1、VR2:可変抵抗素子
Claims (10)
- それぞれのノードに相補的な関係にあるデータを保持可能な双安定回路と、
一方のノードに接続された不揮発性記憶回路とを有し、
前記不揮発性記憶回路は、前記ノードに保持されたデータを記憶したとき、前記ノードに保持されたデータの論理レベルを反転させる、記憶回路。 - 前記不揮発性記憶回路は、可変抵抗素子を含み、
前記ノードに保持されたデータが第1の論理レベルであるとき、前記可変抵抗素子のセット書込みを行い、
前記ノードに保持されたデータが第2の論理レベルであるとき、前記可変抵抗素子のリセット書込みを行う、請求項1に記載の記憶回路。 - 前記不揮発性記憶回路は、前記ノードとソース線との間に直列に接続されたアクセス用トランジスタと可変抵抗素子とを含み、
前記可変抵抗素子のセット書込みを行うとき、アクセス用トランジスタを導通状態にし、前記ノードからソース線へ向かうバイアスを前記可変抵抗素子に印加し、
前記可変抵抗素子のリセット書込みを行うとき、アクセス用トランジスタを導通状態にし、前記ソース線から前記ノードに向かうバイアスを前記可変抵抗素子に印加する、請求項1または2に記載の記憶回路。 - 前記不揮発性記憶回路の記憶されたデータを前記ノードに設定するとき、
セット書込みを行った可変抵抗素子に対してリセット書込みを行い、リセット書込みを行った可変抵抗素子に対してセット書込みを行う、請求項2または3に記載の記憶回路。 - 前記ノードは、トランジスタを介してビット線に接続され、前記可変抵抗素子に記憶されたデータを前記ビット線を介して読み出すことによりベリファイする、請求項2ないし4いずれか1つに記載の記憶回路。
- 記憶回路はさらに、
他のノードに接続された他の不揮発性記憶回路を含み、
当該他の不揮発性記憶回路は、電源投入時に必要とされるブートデータを記憶する、請求項1ないし5いずれか1つに記載の記憶回路。 - 電源投入時、前記他の不揮発性記憶回路に記憶されたブートデータが第1のノードに読み出される、請求項6に記載の記憶回路。
- 前記他の不揮発性記憶回路は、前記他のノードとソース線との間に直列に接続されたアクセス用トランジスタと可変抵抗素子とを含む、請求項6または7に記載の記憶回路。
- 請求項1ないし8いずれか1つに記載された記憶回路と、前記記憶回路を制御するコントローラとを含む、半導体装置。
- 半導体装置はさらに、少なくとも1つのフラッシュメモリを含み、前記コントローラは、前記フラッシュメモリを制御する、請求項9に記載の半導体装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018206352A JP6734904B2 (ja) | 2018-11-01 | 2018-11-01 | 記憶回路 |
TW108112988A TWI700696B (zh) | 2018-11-01 | 2019-04-15 | 記憶電路與半導體裝置 |
KR1020190052155A KR20200050843A (ko) | 2018-11-01 | 2019-05-03 | 기억 회로 및 반도체 장치 |
CN201910373935.7A CN111128272B (zh) | 2018-11-01 | 2019-05-07 | 存储电路与半导体装置 |
US16/548,808 US10978150B2 (en) | 2018-11-01 | 2019-08-22 | Memory circuit and semiconductor device |
KR1020210028552A KR102345149B1 (ko) | 2018-11-01 | 2021-03-04 | 메모리 회로 및 반도체 장치 |
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JP2018206352A JP6734904B2 (ja) | 2018-11-01 | 2018-11-01 | 記憶回路 |
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JP2020071893A true JP2020071893A (ja) | 2020-05-07 |
JP6734904B2 JP6734904B2 (ja) | 2020-08-05 |
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US (1) | US10978150B2 (ja) |
JP (1) | JP6734904B2 (ja) |
KR (2) | KR20200050843A (ja) |
CN (1) | CN111128272B (ja) |
TW (1) | TWI700696B (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110280073A1 (en) * | 2010-05-12 | 2011-11-17 | Industrial Technology Research Institute | Non-volatile static random access memory and operation method thereof |
JP2016033842A (ja) * | 2014-07-31 | 2016-03-10 | 株式会社フローディア | 不揮発性sramメモリセル、および不揮発性半導体記憶装置 |
WO2016080146A1 (ja) * | 2014-11-20 | 2016-05-26 | ソニー株式会社 | 半導体装置 |
Family Cites Families (9)
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JP4262033B2 (ja) * | 2003-08-27 | 2009-05-13 | 株式会社ルネサステクノロジ | 半導体集積回路 |
US7212040B2 (en) * | 2005-05-16 | 2007-05-01 | Intelliserv, Inc. | Stabilization of state-holding circuits at high temperatures |
US7692954B2 (en) * | 2007-03-12 | 2010-04-06 | International Business Machines Corporation | Apparatus and method for integrating nonvolatile memory capability within SRAM devices |
US7961501B1 (en) * | 2008-07-10 | 2011-06-14 | Ryan Technologies, LLC | Radiation sensors and single-event-effects suppression devices |
JP5479656B1 (ja) * | 2012-05-18 | 2014-04-23 | 独立行政法人科学技術振興機構 | 記憶回路 |
KR101666528B1 (ko) | 2012-05-18 | 2016-10-14 | 고쿠리츠켄큐카이하츠호진 카가쿠기쥬츠신코키코 | 쌍안정 회로와 불휘발성 소자를 구비하는 기억 회로 |
WO2016024527A1 (ja) * | 2014-08-12 | 2016-02-18 | 国立研究開発法人科学技術振興機構 | 記憶回路 |
US9553265B1 (en) | 2016-01-14 | 2017-01-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM device with data storage layer having increased height |
JP6430576B2 (ja) * | 2017-04-19 | 2018-11-28 | ウィンボンド エレクトロニクス コーポレーション | 抵抗変化型ランダムアクセスメモリ |
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- 2019-04-15 TW TW108112988A patent/TWI700696B/zh active
- 2019-05-03 KR KR1020190052155A patent/KR20200050843A/ko active Application Filing
- 2019-05-07 CN CN201910373935.7A patent/CN111128272B/zh active Active
- 2019-08-22 US US16/548,808 patent/US10978150B2/en active Active
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- 2021-03-04 KR KR1020210028552A patent/KR102345149B1/ko active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110280073A1 (en) * | 2010-05-12 | 2011-11-17 | Industrial Technology Research Institute | Non-volatile static random access memory and operation method thereof |
JP2016033842A (ja) * | 2014-07-31 | 2016-03-10 | 株式会社フローディア | 不揮発性sramメモリセル、および不揮発性半導体記憶装置 |
WO2016080146A1 (ja) * | 2014-11-20 | 2016-05-26 | ソニー株式会社 | 半導体装置 |
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KR20200050843A (ko) | 2020-05-12 |
KR20210028178A (ko) | 2021-03-11 |
US10978150B2 (en) | 2021-04-13 |
KR102345149B1 (ko) | 2021-12-29 |
JP6734904B2 (ja) | 2020-08-05 |
US20200143882A1 (en) | 2020-05-07 |
TW202018717A (zh) | 2020-05-16 |
CN111128272A (zh) | 2020-05-08 |
CN111128272B (zh) | 2022-10-04 |
TWI700696B (zh) | 2020-08-01 |
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