JP2020017564A - 半導体装置の製造方法および電力変換装置 - Google Patents
半導体装置の製造方法および電力変換装置 Download PDFInfo
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- JP2020017564A JP2020017564A JP2018137714A JP2018137714A JP2020017564A JP 2020017564 A JP2020017564 A JP 2020017564A JP 2018137714 A JP2018137714 A JP 2018137714A JP 2018137714 A JP2018137714 A JP 2018137714A JP 2020017564 A JP2020017564 A JP 2020017564A
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Abstract
Description
図1は、本発明に係る実施の形態1のMOSFET100の構成を示す断面図である。図1に示すようにMOSFET100は、P型(第1導電型)不純物を比較的低濃度(P−)に含むシリコン基板等の半導体基板1上に形成されたP型のエピタキシャル層3上に設けられている。
図5は、本発明に係る実施の形態2のMOSFET200の構成を示す断面図である。なお、図5においては、図1を用いて説明したMOSFET100と同一の構成については同一の符号を付し、重複する説明は省略する。
図9は、本発明に係る実施の形態3のMOSFET200の構成を示す断面図である。なお、図9においては、図1を用いて説明したMOSFET100と同一の構成については同一の符号を付し、重複する説明は省略する。
図14は、本発明に係る実施の形態4のMOSFET400の構成を示す断面図である。なお、図14においては、図9を用いて説明したMOSFET300と同一の構成については同一の符号を付し、重複する説明は省略する。
本実施の形態は、実施の形態1〜4で説明した半導体装置を電力変換装置に適用したものである。実施の形態1〜4で説明した半導体装置は、特定の電力変換装置に限定されるものではないが、以下、実施の形態5として、実施の形態1〜4の半導体装置を、三相のインバータに適用した場合について説明する。
Claims (5)
- 第1導電型の半導体基板と、
前記半導体基板の第1の主面上に設けられた第1導電型のエピタキシャル層と、
前記エピタキシャル層の最表面から内部にかけて設けられた第1導電型の第1の半導体領域と、
前記第1の半導体領域の側面に接して設けられた第2導電型の第2の半導体領域と、
前記第1の半導体領域の上層部に選択的に設けられた第2導電型のソース領域およびドレイン領域と、
前記ソース領域と前記ドレイン領域との間の前記第1の半導体領域上に、ゲート絶縁膜を介して設けられたゲート電極と、
前記第1の半導体領域の底面から前記半導体基板の内部にかけて設けられた第2導電型の第3の半導体領域と、を備えた半導体装置の製造方法であって、
(a)少なくとも前記ソース領域、前記ドレイン領域および前記ゲート電極が形成された状態の前記半導体基板を、前記第1の主面とは反対側の第2の主面を研磨して、前記半導体基板の厚みを薄くする工程と、
(b)研磨後の前記半導体基板の前記第2の主面側から第2導電型の不純物のイオン注入を行い、前記第3の半導体領域を形成する工程と、を備え、
前記工程(b)は、
(b−1)前記第3の半導体領域の第2導電型の不純物濃度が、前記第2の半導体領域の不純物濃度よりも高くなるようにイオン注入を行う工程を含む、半導体装置の製造方法。 - 第1導電型の半導体基板と、
前記半導体基板の第1の主面の最表面から内部にかけて設けられた第1導電型の第1の半導体領域と、
前記第1の半導体領域の側面に接して設けられた第2導電型の第2の半導体領域と、
前記第1の半導体領域の上層部に選択的に設けられた第2導電型のソース領域およびドレイン領域と、
前記ソース領域と前記ドレイン領域との間の前記第1の半導体領域上に、ゲート絶縁膜を介して設けられたゲート電極と、
前記第1の半導体領域の底面から前記半導体基板の内部にかけて設けられた第2導電型の第3の半導体領域と、備えた半導体装置の製造方法であって、
(a)少なくとも前記ソース領域、前記ドレイン領域および前記ゲート電極が形成された状態の前記半導体基板を、前記第1の主面とは反対側の第2の主面を研磨して、前記半導体基板の厚みを薄くする工程と、
(b)研磨後の前記半導体基板の前記第2の主面側から第2導電型の不純物のイオン注入を行い、前記第3の半導体領域を形成する工程と、を備え、
前記工程(b)は、
(b−1)前記第3の半導体領域の第2導電型の不純物濃度が、前記第2の半導体領域の不純物濃度よりも高くなるようにイオン注入を行う工程を含む、半導体装置の製造方法。 - 前記半導体装置は、
前記第2の半導体領域の底面に接すると共に、前記第3の半導体領域の端縁部に接する第2導電型の第4の半導体領域を備え、
前記工程(b)は、
前記第3の半導体領域を形成すると共に、前記第4の半導体領域を形成する工程を含み、
前記工程(b−1)は、
前記第4の半導体領域の第2導電型の不純物濃度が、前記第2の半導体領域の不純物濃度よりも高くなるようにイオン注入を行う工程を含む、請求項1または請求項2記載の半導体装置の製造方法。 - 前記半導体装置は、
研磨後の前記半導体基板の前記第2の主面の最表面から内部にかけて設けられた第1導電型の半導体層を、さらに備え、
(c)研磨後の前記半導体基板の前記第2の主面側から第1導電型の不純物のイオン注入を行い、前記第2の主面の表面内に前記半導体基板よりも不純物濃度が高い前記半導体層形成する工程をさらに備える、請求項1から請求項3の何れか1項に記載の半導体装置の製造方法。 - 請求項1から請求項4の何れか1項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
前記半導体装置を駆動する駆動信号を前記半導体装置に出力する駆動回路と、
前記駆動回路を制御する制御信号を前記駆動回路に出力する制御回路と、を備えた電力変換装置。
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