JP2019530229A - ２０ｎｍ未満のフィンピッチのための新規の自己整合４重パターニングプロセス - Google Patents

２０ｎｍ未満のフィンピッチのための新規の自己整合４重パターニングプロセス Download PDF

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JP2019530229A
JP2019530229A JP2019514071A JP2019514071A JP2019530229A JP 2019530229 A JP2019530229 A JP 2019530229A JP 2019514071 A JP2019514071 A JP 2019514071A JP 2019514071 A JP2019514071 A JP 2019514071A JP 2019530229 A JP2019530229 A JP 2019530229A
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fins
fin
pitch
mandrel
side wall
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JP2019530229A5 (https=
Inventor
スタンレー・ソン
ジェフリー・シュ
ダ・ヤン
カーン・リム
チョー・フェイ・イェプ
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
JP2019514071A 2016-09-20 2017-08-08 ２０ｎｍ未満のフィンピッチのための新規の自己整合４重パターニングプロセス Pending JP2019530229A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/271,043 US10559501B2 (en) 2016-09-20 2016-09-20 Self-aligned quadruple patterning process for Fin pitch below 20nm
US15/271,043 2016-09-20
PCT/US2017/045966 WO2018057141A1 (en) 2016-09-20 2017-08-08 Novel self-aligned quadruple patterning process for fin pitch below 20nm

Publications (2)

Publication Number Publication Date
JP2019530229A true JP2019530229A (ja) 2019-10-17
JP2019530229A5 JP2019530229A5 (https=) 2020-08-27

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JP2019514071A Pending JP2019530229A (ja) 2016-09-20 2017-08-08 ２０ｎｍ未満のフィンピッチのための新規の自己整合４重パターニングプロセス

Country Status (7)

Country Link
US (2) US10559501B2 (https=)
EP (1) EP3516695A1 (https=)
JP (1) JP2019530229A (https=)
KR (1) KR20190046879A (https=)
CN (1) CN109716528A (https=)
BR (1) BR112019005093A2 (https=)
WO (1) WO2018057141A1 (https=)

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JP2022541409A (ja) * 2019-07-17 2022-09-26 インターナショナル・ビジネス・マシーンズ・コーポレーション ナノシートの直接印刷および自己整合ダブル・パターニング

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10763118B2 (en) 2018-07-11 2020-09-01 International Business Machines Corporation Cyclic selective deposition for tight pitch patterning
KR102760190B1 (ko) 2019-05-16 2025-01-23 삼성전자주식회사 반도체 장치 및 그 제조 방법

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JP2013197589A (ja) * 2012-03-19 2013-09-30 Samsung Electronics Co Ltd 電界効果トランジスタの製造方法
WO2015025441A1 (ja) * 2013-08-23 2015-02-26 パナソニック株式会社 半導体集積回路装置
US20150170973A1 (en) * 2013-12-13 2015-06-18 GlobalFoundries, Inc. Methods for fabricating integrated circuits using self-aligned quadruple patterning
JP2015203614A (ja) * 2014-04-14 2015-11-16 株式会社日立ハイテクノロジーズ 荷電粒子線装置および検査装置
US20160181164A1 (en) * 2014-12-18 2016-06-23 International Business Machines Corporation Fin formation on an insulating layer
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WO2015025441A1 (ja) * 2013-08-23 2015-02-26 パナソニック株式会社 半導体集積回路装置
US20150170973A1 (en) * 2013-12-13 2015-06-18 GlobalFoundries, Inc. Methods for fabricating integrated circuits using self-aligned quadruple patterning
JP2015203614A (ja) * 2014-04-14 2015-11-16 株式会社日立ハイテクノロジーズ 荷電粒子線装置および検査装置
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JP7515564B2 (ja) 2019-07-17 2024-07-12 インターナショナル・ビジネス・マシーンズ・コーポレーション ナノシートの直接印刷および自己整合ダブル・パターニング
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Publication number Publication date
US20200161189A1 (en) 2020-05-21
US20180082906A1 (en) 2018-03-22
KR20190046879A (ko) 2019-05-07
US10559501B2 (en) 2020-02-11
WO2018057141A1 (en) 2018-03-29
BR112019005093A2 (pt) 2019-06-04
CN109716528A (zh) 2019-05-03
EP3516695A1 (en) 2019-07-31

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