CN109716528A - 用于小于20nm的鳍间距的新的自对准四重图案化工艺 - Google Patents

用于小于20nm的鳍间距的新的自对准四重图案化工艺 Download PDF

Info

Publication number
CN109716528A
CN109716528A CN201780057284.XA CN201780057284A CN109716528A CN 109716528 A CN109716528 A CN 109716528A CN 201780057284 A CN201780057284 A CN 201780057284A CN 109716528 A CN109716528 A CN 109716528A
Authority
CN
China
Prior art keywords
fin
sidewall spacer
mandrel
spacing
spacer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201780057284.XA
Other languages
English (en)
Inventor
S·宋
J·徐
杨达
K·雷姆
C·F·耶普
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN109716528A publication Critical patent/CN109716528A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

提出了一种制造具有小于20nm的鳍间距的FinFET器件的方法。根据一些实施例，鳍沉积在侧壁间隔件上，侧壁间隔件本身沉积在芯轴上。芯轴可以通过光刻工艺形成，而鳍和侧壁间隔件通过沉积技术形成。

Description

用于小于20nm的鳍间距的新的自对准四重图案化工艺
相关申请的交叉引用
本申请要求2016年09月20日提交的美国申请号15/271,043的优先权，其内容针对所有目的通过引用以其整体并入本文。
技术领域
本申请涉及具有低于二十(20)纳米(nm)间距的FinFET结构的制造。
背景技术
鳍型场效应晶体管(FinFET)越来越多地用于有效地缩放集成电路。具有用作沟道的垂直鳍结构的FinFET在半导体衬底上占据较少的水平空间，并且可以通过一般的半导体图案化工艺形成在逻辑区域和存储区域中。
然而，进一步缩放集成电路的持续的压力已经产生了对形成越来越小的鳍结构的工艺的需求。当前光刻工艺中的光学分辨率的限制不允许形成具有足够小的特征以进一步缩放集成电路的结构。随着对这些设备的特征尺寸的需求持续变小，需要开发用于实现目标尺寸的新工艺。
发明内容
根据一些实施例，一种形成双鳍FinFET器件的鳍的方法包括利用光刻蚀刻工艺形成芯轴；在芯轴上形成侧壁间隔件；以及在侧壁间隔件上形成鳍，其中双鳍FinFET器件形成在侧壁间隔件中的每个侧壁间隔件上。
一种形成多鳍器件的方法可以包括形成具有第一间距和第一宽度的一个或多个芯轴；在一个或多个芯轴的每一侧上形成侧壁间隔件，侧壁间隔件均具有第二宽度；以及在侧壁间隔件的侧面上形成鳍，其中鳍具有小于20nm的间距。
下面结合以下附图更加全面地讨论这些和其他实施例。
附图说明
图1A示出了多鳍FinFET器件的平面图。
图1B示出了多鳍FinFET器件的截面图。
图2图示了用于制造FinFET器件的一个示例过程。
图3图示了用于制造FinFET器件的另一示例过程。
图4图示了根据本发明的一些实施例的用于制造FinFET器件的一个示例过程。
图5图示了根据本发明的一些实施例的用于制造FinFET器件的另一示例过程。
通过参考下面的详细描述，可以最好地理解本公开的实施例及其优点。应当理解，相同的附图标记用于标识一个或多个附图中所示的相同的元件。
具体实施方式
在以下描述中，阐述了描述一些实施例的具体细节。然而，对于本领域技术人员显而易见的是，可以在没有这些具体细节中的一些或全部的情况下实践一些实施例。本文公开的特定实施例是说明性的而非限制性的。本领域技术人员可以认识到其他元件在本公开的范围和精神内，即使本文没有具体描述。
图示本发明的方面和实施例的本描述和附图不应当被视为限制性的，而权利要求限定了受保护的发明。在不脱离本描述和权利要求的精神和范围的情况下，可以进行各种改变。在一些实例中，没有详细示出或描述公知的结构和技术，以免模糊本公开。
图1A和图1B图示了FinFET结构100。如在图1A的平面图中所示的，FinFET结构100包括形成在衬底102上的一个或多个平行的鳍104-1至鳍104-N。栅极结构106沉积在鳍104-1至鳍104-N之上。现代结构可以包括由间距P均匀分离的两个或多个鳍104。FinFET器件可以是nMOS器件或pMOS器件，这取决于鳍104-1到104-N的形成。图1B图示了图1A中所示的结构100的截面图。间距P由两个鳍之间的空间和鳍的宽度限定，如图1A中所示的那样。
尽管图1A和图1B中图示的FinFET结构100极大地增加了器件密度，但是增加器件密度进一步导致对所使用的FinFET结构的小特征尺寸和更小的间距的需求。然而，用于制造具有更高间距的FinFET结构的技术已经超出当前光刻技术的限制。特别地，期望将鳍间距缩放到低于20nm，以缩放逻辑单元高度并因此缩放整体芯片尺寸。
现代光刻在制造具有小的特征的器件时受波长限制。目前，193nm光刻受限于约80nm的特征尺寸。换句话说，193nm光刻工艺可以使用单个光刻曝光和蚀刻工艺制造具有约80nm的最小间距的特征，该最小间距由最小特征宽度加上最小特征间隔限定。为了获得更小的间距尺寸，已经开发了多重图案化光刻(MPL)。已经尝试了两种形式的MPL，一种使用重复的光刻工艺(光刻-蚀刻-光刻或LELE)技术，而另一种基于自对准间隔件处理。在制造FinFET结构的鳍时，自对准间隔件处理是有利的。然而，由于工艺限制，已经证明获得小于20nm的间距是困难的。
自对准间隔件处理通常被称为自对准双重处理(SADP)。在SADP中，通过图案化和蚀刻芯轴材料以光刻方式形成一组芯轴。然后，可以在芯轴的侧壁上形成侧壁间隔件。侧壁间隔件的形成可以通过在芯轴材料之上沉积材料，去除水平表面上所沉积的材料，以及去除芯轴材料，留下侧壁间隔件来实现。侧壁间隔件的沉积可以导致远小于光刻形成芯轴可获得的间隔件宽度的间隔件宽度。然后，可以抛光侧壁间隔件和芯轴，以暴露芯轴和用作去除剩余的芯轴材料的蚀刻掩模的间隔件。
因此，SADP工艺涉及在预先图案化的芯轴的侧壁上形成间隔件作为膜层，从水平表面去除间隔件层，以及去除初始图案化的芯轴材料而留下间隔件本身。由于每一个芯轴有两个侧壁间隔件，因此线密度现在被加倍。因此，SADP适用于以初始光刻间距的一半来限定窄的栅极。理论上，这种间隔件方法可以重复以将间隔件之间的间距连续减半。例如，第二SADP工艺，称为自对准四重图案化(SAQP)，可导致初始形成的芯轴的间距的四分之一的间距。
图2图示了SAQP工艺200。如图2中所示的，芯轴202-1至芯轴202-4以P1的间距沉积。图2图示了芯轴202-1至芯轴202-4，但是可以形成任何数量的芯轴202。如上面所讨论的，使用光刻工艺对芯轴202进行图案化和蚀刻。
然后，在SADP工艺中通过在芯轴202上沉积侧壁材料，去除水平表面上的侧壁材料，以及蚀刻以去除芯轴202，而在芯轴202-1到芯轴202-4上形成侧壁间隔件204-1至204-8。如图2中所示的，侧壁间隔件204-1和204-2形成在芯轴202-1的相对侧上；侧壁间隔件204-3和204-4形成在芯轴202-2的相对侧上；侧壁间隔件204-5和204-6形成在芯轴202-3的相对侧上；并且侧壁间隔件204-7和204-8形成在芯轴202-4的相对侧上。
在侧壁间隔件204上的第二SADP工艺中，侧壁间隔件206-1至206-8和鳍208-1至鳍208-8形成在侧壁间隔件204的侧壁上。如图2中所示的，侧壁间隔件206-1和鳍208-1形成在侧壁间隔件204-1的相对侧上；鳍208-2和侧壁间隔件206-2形成在侧壁间隔件204-2的相对侧上；侧壁间隔件206-3和鳍208-3形成在侧壁间隔件204-3的相对侧上；鳍208-4和侧壁间隔件206-4形成在侧壁间隔件204-4的相对侧上；侧壁间隔件206-4和鳍208-5形成在侧壁间隔件204-5的相对侧上；鳍208-6和侧壁间隔件206-6形成在侧壁间隔件204-6的相对侧上；侧壁间隔件206-7和鳍208-7形成在侧壁间隔件204-7的相对侧上；并且鳍208-8和侧壁间隔件206-8形成在侧壁间隔件204-8的相对侧上。然后，去除间隔件204-1至间隔件204-8以及间隔件206-1至间隔件206-8，留下鳍208-1至鳍208-8。这样，鳍208-1和鳍208-2形成双鳍FinFET器件的一部分；鳍208-3和鳍208-4构成双鳍FinFET器件的一部分；鳍208-5和鳍208-6构成双鳍FinFET器件的一部分；并且鳍208-7和鳍208-8形成双鳍FinFET器件的一部分。如图2中所示的，在侧壁间隔件206的每一个侧壁间隔件上仅形成一个鳍208。
如图2中进一步所示的，在每个连续的SADP工艺中，沉积的器件之间的间距减半。因此，如果芯轴202之间的间距是P1，则间隔件204之间的间距是P1/2，并且单个器件中的鳍208之间的最终间距是P1/4。另外，器件之间的间距是P1。使用193nm光刻工艺的限制，P1为80nm并且鳍之间的间距为20nm。因此，如图2中所示的SAQP不能制造鳍之间小于20nm的间距尺寸。
图3图示了自对准八重工艺(SAOP)，其可以利用193nm光刻工艺实现小于20nm的间距。通过三个连续的SADP工艺执行SAOP，产生的间距是芯轴之间的间距的1/8。如图3中所示的，使用光刻工艺来图案化芯轴302-1和芯轴302-2。芯轴302以间距P2沉积。如图3中所示的，在第一SADP工艺中，侧壁间隔件304然后沉积在芯轴302上。因此，侧壁间隔件304-1和304-2形成在芯轴302-1的相对侧上，并且侧壁间隔件304-3和304-4形成在芯轴302-2的相对侧上。然后去除芯轴302，留下侧壁间隔件304。如图3中所示的，侧壁间隔件304具有P2/2的间距。在第二SADP工艺中，侧壁间隔件306形成在侧壁间隔件304上并且侧壁间隔件304被去除。如图3中所示的，侧壁间隔件306-1和306-2形成在侧壁间隔件304-1的相对侧上；侧壁间隔件306-3和306-4形成在侧壁间隔件304-2的相对侧上；侧壁间隔件306-5和306-6形成在侧壁间隔件304-3的相对侧上；并且侧壁间隔件306-7和306-8形成在侧壁间隔件304-4的相对侧上。侧壁间隔件306之间的间距现在是P2/4。
在又一第三SADP工艺中，在侧壁间隔件306上形成侧壁间隔件307和鳍308，之后去除间隔件307和间隔件306，留下鳍308。如图3中所示的，侧壁间隔件307-1和鳍308-1形成在侧壁间隔件306-1的相对侧上；鳍308-2和侧壁间隔件307-2形成在侧壁间隔件306-2的相对侧上；侧壁间隔件307-3和鳍308-3形成在侧壁间隔件306-3的相对侧上；鳍308-4和侧壁间隔件307-4形成在侧壁间隔件306-4的相对侧上；侧壁间隔件307-5和鳍308-5形成在侧壁间隔件306-5的相对侧上；鳍308-6和侧壁间隔件307-6形成在侧壁间隔件306-6的相对侧上；侧壁间隔件307-7和鳍308-7形成在侧壁间隔件306-7的相对侧上；并且鳍308-8和侧壁间隔件307-8形成在侧壁间隔件306-8的相对侧上。然后，在鳍308和侧壁间隔件307之间产生的间距为P2/8。同样，在侧壁间隔件306中的每个上仅形成一个鳍308。
如果P2是例如128nm，那么P2/2是64nm；P2/4为32nm；并且P2/8是16nm。因此，通过器件分离(在使用SAOP工艺去除32nm的虚设鳍或侧壁间隔件307之后)可以实现16nm的间距。然而，实现所需的第三SADP工艺需要太多的工艺步骤，增加了成本并使工艺复杂化，并且难以在材料沉积工艺的约束下实现。
图4图示了根据本发明一些实施例的用于实现具有小于20nm的间距的双鳍器件的SAQP工艺的示例。如图4中所示的，芯轴402在光刻工艺中沉积。在图4中图示了芯轴402-1和芯轴402-2。芯轴402-1和芯轴402-2以间距P3和宽度W1沉积。侧壁间隔件404沉积在芯轴402的侧壁上。因此，侧壁间隔件404-1和404-2形成在芯轴402-1的相对侧上，并且侧壁间隔件404-3和404-4形成在芯轴402-2的相对侧上。然而，侧壁间隔件404的宽度W2被布置成影响鳍406的最终间距，而不是将侧壁间隔件404的宽度W2布置成使得侧壁间隔件404之间的间距是P3/2。
如图4中所示的，鳍406形成在侧壁间隔件404的侧壁上。如所图示的，鳍406-1和鳍406-2形成在侧壁间隔件404-1的相对侧上；鳍406-3和鳍406-4形成在侧壁间隔件404-2的相对侧上；鳍406-5和鳍506-6形成在侧壁间隔件404-3的相对侧上；并且鳍406-7和鳍406-8形成在侧壁间隔件404-4的相对侧上。在一些实施例中，侧壁间隔件404的宽度W2和鳍406的宽度W3是相同的。
如图4中进一步图示的，芯轴402可以以P3的间距形成。每个器件中的鳍406具有P的间距，并且器件具有D的间距间隔。作为示例，如果侧壁间隔件404的宽度W2和鳍406的W2之和为16nm，则可以使间距P为16nm。作为示例，如果W2和W3都为8nm(这是使用7nm工艺技术沉积侧壁材料的可实现尺寸)，则间距P为16nm。通过变化芯轴402的宽度W1和间隔件W2的宽度，侧壁间隔件404PS的间距可以被设置为P3/2。产生的双鳍器件之间的间隔D由W1和W2之和给出。然而，芯轴402之间的间隔可能不会导致每个侧壁间隔件404之间的均匀距离。
因此，如图4中所示的，在包括利用光刻蚀刻工艺形成具有宽度W1和间距P3的芯轴402的工艺中，形成具有小间距(间距小于20nm)的鳍。侧壁间隔件404通过在芯轴402的侧面上沉积材料而形成，并且芯轴材料被去除以留下侧壁间隔件404。侧壁间隔件404均具有宽度W2并且侧壁间隔件具有PS的间距。然后，在间隔件404的侧壁上形成鳍406，其中每个间隔件404用于单个双鳍器件的形成。结果，当间隔件404被去除时，就不会去除沉积在侧壁上的鳍406(即，没有虚设间隔件去除)。在一些实施例中，芯轴间距P3可以用于将NMOS FinFET与PMOS FinFET器件分离。
图4中图示的本发明的示例实施例可以制造小于20nm的鳍间距，这主要是因为鳍间距仅取决于在特定宽度内沉积侧壁间隔件404和鳍406的能力。在7nm技术中，那些沉积宽度可以低至7nm，并且8nm或以上的宽度是可获得的。器件之间的间隔D仍然取决于形成芯轴402所涉及的工艺限制。
图5图示了根据本发明一些实施例的用于制造多鳍FinFET器件的过程的示例，其中鳍的数量大于2。尽管由于工艺技术的限制，可能不容易实现小于20nm的鳍间距，但是图5中所图示的过程可以用于制造鳍间距可以大于20nm的多鳍器件。
如图5中所示的，芯轴502通过光刻和蚀刻工艺形成。芯轴502(图示了芯轴502-1至芯轴502-4)具有P4的间距和W1的宽度(在光刻工艺的分辨率的限制内)。如进一步所示的，侧壁间隔件504形成在芯轴502上。具体地，侧壁间隔件504-1和504-3形成在芯轴502-1的相对侧上；侧壁间隔件504-3和504-4形成在芯轴502-2的相对侧上；侧壁间隔件504-5和504-6形成在芯轴502-3的相对侧上；并且504-7和504-8形成在芯轴502-4的相对侧上。
如进一步所示的，鳍506和牺牲侧壁间隔件507形成在侧壁间隔件504上。图5图示了三鳍器件的制造，然而，也可以使用在单个芯轴502上的侧壁504来制造四鳍器件。可以使用来自相邻芯轴502的侧壁504来制造具有大于四个的鳍的器件。
在图5中所图示的示例三鳍器件中，每个器件的鳍可以跨越相邻的芯轴502。如图5中所示的，鳍506-1和鳍506-2形成在侧壁间隔件504-1的相对侧上。在形成鳍506期间，在侧壁间隔件504-2的相对侧上形成牺牲间隔件507-1和507-2并将其去除。鳍506-3和鳍506-4形成在侧壁间隔件504-3的相对侧上，并且鳍506-5(形成包括鳍506-3、506-4和506-5的器件的第三鳍)形成在侧壁间隔件504-4的第一侧上。牺牲间隔件507-3形成在侧壁间隔件504-4的第二侧上。如图5中进一步图示的，牺牲侧壁间隔件507-4和鳍506-6形成在侧壁间隔件504-5的相对侧上；鳍506-7和鳍506-8形成在侧壁间隔件504-6的相对侧上；牺牲侧壁间隔件507-5和507-6形成在侧壁间隔件504-7的相对侧上；并且鳍506-9和鳍506-10形成在侧壁间隔件504-8的相对侧上。
因此，如图5中所示的，假设可以容许更大的鳍间距，则可以根据本发明的一些实施例形成具有大于两个的鳍的器件。如图5中所示的，鳍506之间的间距由侧壁间隔件504的宽度W2确定。因此，鳍间距(在图5中作为示例示作P4/4)由侧壁间隔件504的宽度W2和侧壁间隔件w3的宽度W3之和给出。可以调节芯轴502的宽度W1以制造多鳍器件的总间距P4/4。在一些实施例中，间隔件504的宽度W2和鳍506的宽度W3相同。
在前面的说明书中，已经参考附图描述了各种实施例。然而，显而易见的是，可以在不脱离如在随后的权利要求中所阐述的本发明的更宽范围的情况下，对其进行各种修改和改变，并且可以实施附加的实施例。因此，说明书和附图被认为是说明性的而不是限制性的。

Claims (21)

1.一种形成双鳍FinFET器件的鳍的方法，包括：
利用光刻蚀刻工艺形成芯轴；
在所述芯轴上形成侧壁间隔件；以及
在所述侧壁间隔件上形成鳍，
其中所述双鳍FinFET器件形成在所述侧壁间隔件中的每一个侧壁间隔件上。
2.根据权利要求1所述的方法，其中所述双鳍FinFET器件的间距小于20nm。
3.根据权利要求1所述的方法，其中一对所述双鳍FinFET器件之间的间隔由所述芯轴的宽度确定。
4.根据权利要求1所述的方法，其中芯轴之间的距离可以将nMOS FinFET器件与pMOSFinFET器件分离。
5.根据权利要求1所述的方法，其中所述双鳍FinFET器件的间距由侧壁间隔件宽度和鳍宽度确定。
6.根据权利要求1所述的方法，还包括去除所述芯轴和所述侧壁间隔件。
7.一种形成多鳍器件的方法，包括：
形成具有第一间距和第一宽度的一个或多个芯轴；
在所述一个或多个芯轴的每一侧上形成侧壁间隔件，所述侧壁间隔件均具有第二宽度；以及
在所述侧壁间隔件的侧面上形成鳍，其中所述鳍具有小于20nm的间距。
8.根据权利要求7所述的方法，其中利用光刻曝光和蚀刻工艺形成所述芯轴。
9.根据权利要求7所述的方法，其中利用材料沉积技术沉积所述侧壁间隔件和所述鳍。
10.根据权利要求9所述的方法，其中所述材料沉积技术是7nm技术。
11.根据权利要求7所述的方法，还包括去除所述芯轴和所述侧壁间隔件以留下所述鳍。
12.根据权利要求7所述的方法，其中所述多鳍器件是双鳍器件，所述双鳍器件形成在所述侧壁间隔件中的一个侧壁间隔件上。
13.根据权利要求12所述的方法，其中根据所述芯轴的所述宽度分离相邻的双鳍器件。
14.根据权利要求7所述的方法，其中所述多鳍器件包括形成在相邻的侧壁间隔件上的多于两个的鳍。
15.一种多鳍器件，包括：
多个鳍，所述多个鳍通过沉积形成在侧壁间隔件上，所述侧壁间隔件已被芯轴分离，
其中所述多个鳍的间距小于20nm。
16.根据权利要求15所述的多鳍器件，其中所述多个鳍包括形成在一个侧壁间隔件的相对侧上的两个鳍。
17.根据权利要求16所述的多鳍器件，其中所述两个鳍与另一双鳍器件分离。
18.根据权利要求15所述的多鳍器件，其中所述多个鳍包括形成在相邻侧壁间隔件的侧面上的多于两个的鳍。
19.根据权利要求15所述的多鳍器件，其中所述侧壁间隔件被去除。
20.一种多鳍器件，包括：
用于提供间距小于20nm的多个鳍的装置。
21.根据权利要求20所述的多鳍器件，其中用于提供多个鳍的装置包括：
用于沉积芯轴的装置；和
用于在所述芯轴上沉积侧壁间隔件的装置。
CN201780057284.XA 2016-09-20 2017-08-08 用于小于20nm的鳍间距的新的自对准四重图案化工艺 Pending CN109716528A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/271,043 2016-09-20
US15/271,043 US10559501B2 (en) 2016-09-20 2016-09-20 Self-aligned quadruple patterning process for Fin pitch below 20nm
PCT/US2017/045966 WO2018057141A1 (en) 2016-09-20 2017-08-08 Novel self-aligned quadruple patterning process for fin pitch below 20nm

Publications (1)

Publication Number Publication Date
CN109716528A true CN109716528A (zh) 2019-05-03

Family

ID=59631887

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780057284.XA Pending CN109716528A (zh) 2016-09-20 2017-08-08 用于小于20nm的鳍间距的新的自对准四重图案化工艺

Country Status (7)

Country Link
US (2) US10559501B2 (zh)
EP (1) EP3516695A1 (zh)
JP (1) JP2019530229A (zh)
KR (1) KR20190046879A (zh)
CN (1) CN109716528A (zh)
BR (1) BR112019005093A2 (zh)
WO (1) WO2018057141A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10763118B2 (en) 2018-07-11 2020-09-01 International Business Machines Corporation Cyclic selective deposition for tight pitch patterning
KR20200132183A (ko) 2019-05-16 2020-11-25 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11257681B2 (en) 2019-07-17 2022-02-22 International Business Machines Corporation Using a same mask for direct print and self-aligned double patterning of nanosheets

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915332A (zh) * 2013-01-08 2014-07-09 中芯国际集成电路制造(上海)有限公司 图案的形成方法
TW201428824A (zh) * 2012-12-03 2014-07-16 Applied Materials Inc 半導體裝置處理工具及用於將基板型樣化的方法
CN104347421A (zh) * 2013-08-07 2015-02-11 中芯国际集成电路制造(北京)有限公司 鳍式场效应管的形成方法
US20160181164A1 (en) * 2014-12-18 2016-06-23 International Business Machines Corporation Fin formation on an insulating layer
US20160240386A1 (en) * 2015-02-13 2016-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Self-Aligned Multiple Spacer Patterning Process

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6762448B1 (en) * 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US7638381B2 (en) * 2005-10-07 2009-12-29 International Business Machines Corporation Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby
US8669186B2 (en) 2012-01-26 2014-03-11 Globalfoundries Inc. Methods of forming SRAM devices using sidewall image transfer techniques
KR101823105B1 (ko) * 2012-03-19 2018-01-30 삼성전자주식회사 전계 효과 트랜지스터의 형성 방법
US8492228B1 (en) * 2012-07-12 2013-07-23 International Business Machines Corporation Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers
US9093556B2 (en) 2012-08-21 2015-07-28 Stmicroelectronics, Inc. Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods
US9123654B2 (en) 2013-02-15 2015-09-01 International Business Machines Corporation Trilayer SIT process with transfer layer for FINFET patterning
US9040371B2 (en) 2013-08-07 2015-05-26 International Business Machines Corporation Integration of dense and variable pitch fin structures
WO2015025441A1 (ja) * 2013-08-23 2015-02-26 パナソニック株式会社 半導体集積回路装置
US9171764B2 (en) * 2013-12-13 2015-10-27 GlobalFoundries, Inc. Methods for fabricating integrated circuits using self-aligned quadruple patterning
KR20150101398A (ko) 2014-02-24 2015-09-03 아이엠이씨 브이제트더블유 기판 내 반도체 장치의 핀 구조체 제조방법
JP6227466B2 (ja) * 2014-04-14 2017-11-08 株式会社日立ハイテクノロジーズ 荷電粒子線装置および検査装置
US9209038B2 (en) 2014-05-02 2015-12-08 GlobalFoundries, Inc. Methods for fabricating integrated circuits using self-aligned quadruple patterning
US20150372107A1 (en) 2014-06-18 2015-12-24 Stmicroelectronics, Inc. Semiconductor devices having fins, and methods of forming semiconductor devices having fins
TWI540650B (zh) 2014-08-06 2016-07-01 聯華電子股份有限公司 鰭狀場效電晶體元件製造方法
US9209279B1 (en) 2014-09-12 2015-12-08 Applied Materials, Inc. Self aligned replacement fin formation
JP6502705B2 (ja) * 2015-03-03 2019-04-17 キヤノン株式会社 形成方法
US9287135B1 (en) 2015-05-26 2016-03-15 International Business Machines Corporation Sidewall image transfer process for fin patterning
US9640633B1 (en) * 2015-12-18 2017-05-02 International Business Machines Corporation Self aligned gate shape preventing void formation
US9793271B1 (en) * 2016-04-29 2017-10-17 International Business Machines Corporation Semiconductor device with different fin pitches
US9806155B1 (en) * 2016-05-05 2017-10-31 International Business Machines Corporation Split fin field effect transistor enabling back bias on fin type field effect transistors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201428824A (zh) * 2012-12-03 2014-07-16 Applied Materials Inc 半導體裝置處理工具及用於將基板型樣化的方法
CN103915332A (zh) * 2013-01-08 2014-07-09 中芯国际集成电路制造(上海)有限公司 图案的形成方法
CN104347421A (zh) * 2013-08-07 2015-02-11 中芯国际集成电路制造(北京)有限公司 鳍式场效应管的形成方法
US20160181164A1 (en) * 2014-12-18 2016-06-23 International Business Machines Corporation Fin formation on an insulating layer
US20160240386A1 (en) * 2015-02-13 2016-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Self-Aligned Multiple Spacer Patterning Process

Also Published As

Publication number Publication date
EP3516695A1 (en) 2019-07-31
US20200161189A1 (en) 2020-05-21
BR112019005093A2 (pt) 2019-06-04
WO2018057141A1 (en) 2018-03-29
US20180082906A1 (en) 2018-03-22
KR20190046879A (ko) 2019-05-07
JP2019530229A (ja) 2019-10-17
US10559501B2 (en) 2020-02-11

Similar Documents

Publication Publication Date Title
EP3182461B1 (en) Method for fabricating finfet technology with locally higher fin-to-fin pitch
CN104867824B (zh) 具有变化栅极结构的集成电路及其制法
US8569125B2 (en) FinFET with improved gate planarity
US9177820B2 (en) Sub-lithographic semiconductor structures with non-constant pitch
US9171764B2 (en) Methods for fabricating integrated circuits using self-aligned quadruple patterning
US20160093502A1 (en) Fin cut for tight fin pitch by two different sit hard mask materials on fin
CN103137459A (zh) 利用多侧壁图像转移技术在结构中图案化特征的方法
JP7422168B2 (ja) 半導体デバイス
US9263442B2 (en) Replacement gate structures and methods of manufacturing
DE102017117863B4 (de) Integrierte Schaltung mit einer Gatestruktur und Herstellungsverfahren
US9214356B2 (en) Mechanisms for forming patterns
CN109716528A (zh) 用于小于20nm的鳍间距的新的自对准四重图案化工艺
US20150035081A1 (en) Inverse side-wall image transfer
US20160268406A1 (en) Single-electron transistor and its fabrication method
US9006110B1 (en) Method for fabricating patterned structure of semiconductor device
TWI645516B (zh) 形成ｓａｄｐ於ｓｒａｍ上及ｓａｑｐ於邏輯上的裝置及方法
US9276115B2 (en) Semiconductor devices and methods of manufacture
US11721582B2 (en) Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits
US20150179786A1 (en) Molded dielectric nanostructure
CN110148585A (zh) 金属栅极及其制造方法
CN107039347A (zh) 使用虚设栅极形成具有应力的外延层
Gaben et al. Hydrogen silsesquioxane tri-dimensional advanced patterning concepts for high density of integration in sub-7 nm nodes
KR20200144455A (ko) 평면도에서 2차원 형상을 갖는 수직 전계 효과 트랜지스터를 위한 핀 구조체

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190503

WD01 Invention patent application deemed withdrawn after publication