JP2019530229A5 - - Google Patents

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Publication number
JP2019530229A5
JP2019530229A5 JP2019514071A JP2019514071A JP2019530229A5 JP 2019530229 A5 JP2019530229 A5 JP 2019530229A5 JP 2019514071 A JP2019514071 A JP 2019514071A JP 2019514071 A JP2019514071 A JP 2019514071A JP 2019530229 A5 JP2019530229 A5 JP 2019530229A5
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JP
Japan
Prior art keywords
fin
sidewall spacer
forming
fins
mandrel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2019514071A
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English (en)
Japanese (ja)
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JP2019530229A (ja
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Publication date
Priority claimed from US15/271,043 external-priority patent/US10559501B2/en
Application filed filed Critical
Publication of JP2019530229A publication Critical patent/JP2019530229A/ja
Publication of JP2019530229A5 publication Critical patent/JP2019530229A5/ja
Pending legal-status Critical Current

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JP2019514071A 2016-09-20 2017-08-08 20nm未満のフィンピッチのための新規の自己整合4重パターニングプロセス Pending JP2019530229A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/271,043 US10559501B2 (en) 2016-09-20 2016-09-20 Self-aligned quadruple patterning process for Fin pitch below 20nm
US15/271,043 2016-09-20
PCT/US2017/045966 WO2018057141A1 (en) 2016-09-20 2017-08-08 Novel self-aligned quadruple patterning process for fin pitch below 20nm

Publications (2)

Publication Number Publication Date
JP2019530229A JP2019530229A (ja) 2019-10-17
JP2019530229A5 true JP2019530229A5 (https=) 2020-08-27

Family

ID=59631887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019514071A Pending JP2019530229A (ja) 2016-09-20 2017-08-08 20nm未満のフィンピッチのための新規の自己整合4重パターニングプロセス

Country Status (7)

Country Link
US (2) US10559501B2 (https=)
EP (1) EP3516695A1 (https=)
JP (1) JP2019530229A (https=)
KR (1) KR20190046879A (https=)
CN (1) CN109716528A (https=)
BR (1) BR112019005093A2 (https=)
WO (1) WO2018057141A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10763118B2 (en) 2018-07-11 2020-09-01 International Business Machines Corporation Cyclic selective deposition for tight pitch patterning
KR102760190B1 (ko) 2019-05-16 2025-01-23 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11257681B2 (en) 2019-07-17 2022-02-22 International Business Machines Corporation Using a same mask for direct print and self-aligned double patterning of nanosheets

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6762448B1 (en) * 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US7638381B2 (en) * 2005-10-07 2009-12-29 International Business Machines Corporation Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby
US8669186B2 (en) 2012-01-26 2014-03-11 Globalfoundries Inc. Methods of forming SRAM devices using sidewall image transfer techniques
KR101823105B1 (ko) * 2012-03-19 2018-01-30 삼성전자주식회사 전계 효과 트랜지스터의 형성 방법
US8492228B1 (en) * 2012-07-12 2013-07-23 International Business Machines Corporation Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers
US9093556B2 (en) 2012-08-21 2015-07-28 Stmicroelectronics, Inc. Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods
WO2014088918A1 (en) * 2012-12-03 2014-06-12 Applied Materials, Inc Semiconductor device processing tools and methods for patterning substrates
US9123654B2 (en) 2013-02-15 2015-09-01 International Business Machines Corporation Trilayer SIT process with transfer layer for FINFET patterning
US9040371B2 (en) 2013-08-07 2015-05-26 International Business Machines Corporation Integration of dense and variable pitch fin structures
CN104347421A (zh) * 2013-08-07 2015-02-11 中芯国际集成电路制造(北京)有限公司 鳍式场效应管的形成方法
WO2015025441A1 (ja) * 2013-08-23 2015-02-26 パナソニック株式会社 半導体集積回路装置
US9171764B2 (en) * 2013-12-13 2015-10-27 GlobalFoundries, Inc. Methods for fabricating integrated circuits using self-aligned quadruple patterning
US9391141B2 (en) 2014-02-24 2016-07-12 Imec Vzw Method for producing fin structures of a semiconductor device in a substrate
JP6227466B2 (ja) * 2014-04-14 2017-11-08 株式会社日立ハイテクノロジーズ 荷電粒子線装置および検査装置
US9209038B2 (en) 2014-05-02 2015-12-08 GlobalFoundries, Inc. Methods for fabricating integrated circuits using self-aligned quadruple patterning
US20150372107A1 (en) 2014-06-18 2015-12-24 Stmicroelectronics, Inc. Semiconductor devices having fins, and methods of forming semiconductor devices having fins
TWI540650B (zh) 2014-08-06 2016-07-01 聯華電子股份有限公司 鰭狀場效電晶體元件製造方法
US9209279B1 (en) 2014-09-12 2015-12-08 Applied Materials, Inc. Self aligned replacement fin formation
US9530701B2 (en) 2014-12-18 2016-12-27 International Business Machines Corporation Method of forming semiconductor fins on SOI substrate
US9472414B2 (en) * 2015-02-13 2016-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned multiple spacer patterning process
JP6502705B2 (ja) * 2015-03-03 2019-04-17 キヤノン株式会社 形成方法
US9287135B1 (en) 2015-05-26 2016-03-15 International Business Machines Corporation Sidewall image transfer process for fin patterning
US9640633B1 (en) * 2015-12-18 2017-05-02 International Business Machines Corporation Self aligned gate shape preventing void formation
US9793271B1 (en) * 2016-04-29 2017-10-17 International Business Machines Corporation Semiconductor device with different fin pitches
US9806155B1 (en) * 2016-05-05 2017-10-31 International Business Machines Corporation Split fin field effect transistor enabling back bias on fin type field effect transistors

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