JP2019161190A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 238000005229 chemical vapour deposition Methods 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000020169 heat generation Effects 0.000 description 5
- 239000012141 concentrate Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000000034 method Methods 0.000 description 4
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- 239000007788 liquid Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
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- 238000002161 passivation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
Description
第1実施形態に係る半導体装置は、終端領域に位置する、ソース領域が形成されていないメサ部における、ソース電極のコンタクトの幅を、ソース領域が形成されたメサ部のソース電極のコンタクトの幅よりも広くすることにより、回復動作時のホール排出抵抗の低減を図ったものである。以下に、その詳細を説明する。
第2実施形態は、上述した第1実施形態に係る半導体装置1において、トレンチ長手方向の終端部における、セルCのソース領域22が形成されていない領域にあるコンタクト32の幅も広げることにより、逆回復時における終端部からのホール排出抵抗の低減を図ったものである。以下、上述した第1実施形態と異なる部分を説明する。
第3実施形態は、上述した第1実施形態に係る半導体装置1において、コンタクト32を、ソース電極26の一部であるメタルにより形成するのではなく、p+形の半導体領域により形成するようにしたものである。以下、上述した第1実施形態と異なる部分を説明する。
第4実施形態は、上述した第1実施形態を変形して、ゲート電極18の下方に埋め込みの電極を形成したトレンチフィールドプレート構造にしたものである。以下、上述した第1実施形態と異なる部分を説明する。
第5実施形態は、上述した第2実施形態と第4実施形態とを組み合わせたものであり、第2実施形態に係るトレンチ長手方向の終端部に幅広のコンタクト32cを形成した半導体装置1を、トレンチフィールドプレート構造にしたものである。
第6実施形態は、上述した第3実施形態と第4実施形態とを組み合わせたものであり、第3実施形態に係るトレンチ長手方向の終端部に幅広のコンタクト32cを形成した半導体装置1を、トレンチフィールドプレート構造にしたものである。別な見方をすれば、上述した第5実施形態における半導体装置1において、コンタクト32をメタルではなく、p+形の半導体領域により形成したものである。
第7実施形態は、上述した第4実施形態の半導体装置1において、セルCの形成されない終端領域の近傍にあるメサ部における幅W1のコンタクト32aを、セルCの形成されるメサ部における幅W2のコンタクト32bよりも、深い位置まで形成し、より一層のホールの排出抵抗の低減を図ったものである。以下、上述した第4実施形態と異なる部分を説明する。
第8実施形態は、上述した第2実施形態と第7実施形態とを組み合わせたものであり、第7実施形態に係る半導体装置1のコンタクト32におけるトレンチ長手方向の終端部に、幅広のコンタクト32cを形成したものである。以下、上述した第7実施形態と異なる部分を説明する。
Claims (10)
- 第1導電形の第1半導体領域と、
前記第1半導体領域の上に形成された第2導電形のベース領域と、
前記ベース領域を貫通して前記第1半導体領域に達する、複数のゲート電極と、
前記複数のゲート電極のそれぞれの周囲に形成された、複数のゲート絶縁膜と、
前記複数のゲート絶縁膜の間である複数の領域のうち、第1導電形のソース領域が形成された第1領域と、
前記複数の領域のうち、前記第1領域の終端領域に位置し、前記ソース領域が形成されていない第2領域と、
前記第1領域に形成されて、前記ベース領域とソース電極とを電気的に接続する、第1の幅の第1コンタクトと、
前記第2領域に形成されて、前記ベース領域と前記ソース電極とを電気的に接続する、前記第1の幅よりも広い第2の幅の第2コンタクトと、
を備える、半導体装置。 - 前記第1コンタクトと前記第2コンタクトは、メタルにより形成されている、請求項1に記載の半導体装置。
- 前記第1コンタクトが延びる方向の終端部に、前記第1の幅よりも広い第3の幅で形成された第3コンタクトを、さらに備える請求項1又は請求項2に記載の半導体装置。
- 前記第1コンタクト及び前記第2コンタクトは、第2導電形の第2半導体領域により形成されている、請求項1に記載の半導体装置。
- 前記複数のゲート電極のそれぞれの下方における、前記第1半導体領域に埋め込まれた、複数のフィールドプレート電極をさらに備える請求項1乃至請求項4のいずれかに記載の半導体装置。
- 前記複数のフィールドプレート電極は、前記ゲート電極又は前記ソース電極に接続されている、請求項5に記載の半導体装置。
- 前記複数のフィールドプレート電極の周囲には、前記ゲート絶縁膜よりも厚いフィールドプレート絶縁膜が形成されている、請求項5又は請求項6に記載の半導体装置。
- 前記第1コンタクト、前記第2コンタクト及び前記第3コンタクトは、第2導電形の第3半導体領域により形成されている、請求項3に記載の半導体装置。
- 前記第1領域に形成される前記第1コンタクトの深さよりも、前記第2領域に形成される前記第2コンタクトの深さの方が深い、請求項1又は請求項2に記載の半導体装置。
- 前記第1領域に形成される前記第1コンタクトの深さよりも、前記第2領域に形成される前記第2コンタクトの深さの方が深く、且つ、
前記第1領域に形成される前記第1コンタクトの深さよりも、前記第1コンタクトが延びる方向の終端部に形成された前記第3コンタクトの深さの方が深い、
請求項3に記載の半導体装置。
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