JP2019050363A - 半導体パッケージ構造 - Google Patents
半導体パッケージ構造 Download PDFInfo
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- JP2019050363A JP2019050363A JP2018157153A JP2018157153A JP2019050363A JP 2019050363 A JP2019050363 A JP 2019050363A JP 2018157153 A JP2018157153 A JP 2018157153A JP 2018157153 A JP2018157153 A JP 2018157153A JP 2019050363 A JP2019050363 A JP 2019050363A
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- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
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- JOIPGYAFSWSMAB-UHFFFAOYSA-N CCO[Si](OCC)(OCC)CCCOCC1CO1.CCO[Si](OCC)(OCC)CCCOCC1CO1 Chemical compound CCO[Si](OCC)(OCC)CCCOCC1CO1.CCO[Si](OCC)(OCC)CCCOCC1CO1 JOIPGYAFSWSMAB-UHFFFAOYSA-N 0.000 description 1
- 229910002651 NO3 Inorganic materials 0.000 description 1
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- 150000004645 aluminates Chemical class 0.000 description 1
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- 238000006731 degradation reaction Methods 0.000 description 1
- GAURFLBIDLSLQU-UHFFFAOYSA-N diethoxy(methyl)silicon Chemical compound CCO[Si](C)OCC GAURFLBIDLSLQU-UHFFFAOYSA-N 0.000 description 1
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- 239000002245 particle Substances 0.000 description 1
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- ZHCVSLKFILZSDK-UHFFFAOYSA-I potassium silicon(4+) pentafluoride Chemical compound [F-].[K+].[Si+4].[F-].[F-].[F-].[F-] ZHCVSLKFILZSDK-UHFFFAOYSA-I 0.000 description 1
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- FRGPKMWIYVTFIQ-UHFFFAOYSA-N triethoxy(3-isocyanatopropyl)silane Chemical compound CCO[Si](OCC)(OCC)CCCN=C=O FRGPKMWIYVTFIQ-UHFFFAOYSA-N 0.000 description 1
- RXRIEAKKQPAUKB-UHFFFAOYSA-N trimethoxy-[3-(oxiran-2-ylmethoxy)propyl]silane Chemical compound CO[Si](OC)(OC)CCCOCC1CO1.CO[Si](OC)(OC)CCCOCC1CO1 RXRIEAKKQPAUKB-UHFFFAOYSA-N 0.000 description 1
- 238000004383 yellowing Methods 0.000 description 1
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- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H05K2201/09009—Substrate related
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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Abstract
【解決手段】半導体パッケージ構造10Aは第1の基板101と第2の基板102と半導体チップ103とを備え、第1の基板101は、第2の基板102上に配置され、半導体チップ103は第1の基板101上に配置される。半導体パッケージ10Aは、はんだ収容部を兼ねる2つの切り欠き102C、102Eを有する。基板の開口部にこれらの切欠き102C、102Eを使って半導体パッケージの下部を回路基板に沈めて接合することで基板表面からの突出を抑えると共に、半導体パッケージ10Aが回路基板上の半田をオフセットさせることはなくなる。
【選択図】図1B
Description
基板は、第1の基板と第2の基板とを含む。
第1の基板は、台座、第1の突出部および第2の突出部を含む。台座は、第1の表面、第1の側面及び第2の側面を含む。第1の突出部および第2の突出部は、第1の側面および第2の側面からそれぞれ延出しており、第1の接続面および第2の接続面をそれぞれ含む。第1の接続面および第2の接続面は、第1の側面および第2の側面にそれぞれ接続される。
第2の基板は、第2の表面を含む。第1の基板は、第2の表面の一部に配置される。第1の基板と第2の基板は、一体的に形成される。
半導体チップは、台座の第1の表面に配置される。
基板は、第1の基板と第2の基板とを含む。
第1の基板は、第1の表面と第1の裏面を含む。
第2の基板は、第2の表面、第2の裏面、下表面、および複数の第1の半田収容部を含む。第1の半田収容部は、下表面に配置される。第1の基板は、第2の表面に配置される。第1の基板と第2の基板とは電気的に接続される。第1の基板と第2の基板は、一体的に形成される。
半導体チップは、第1の表面に配置され、第1の基板に電気的に接続される。
10A' 電子デバイス
101 第1の基板
102 第2の基板
103 半導体チップ
104 コロイド
105 回路基板
101A 台座
101B 第1の突出部
101C 第2の突出部
101D 配線パターン層
102A 第2の表面
102B 裏面
102C 第1の切り欠け
102D 別の配線パターン層
102E 第2の切り欠け
105A 開口
105AA 第1の領域
105AB 第2の領域
105B 上面
105C 表面
1011 第1の表面
1012 第1の側面
1013 第2の側面
1014 第1の接続面
1015 第2の接続面
1031 半田
1051 第1の支持部
1052 第2の支持部
1051A 第1の電極
1052A 第2の電極
20A 半導体パッケージ構造
201 第1の基板
202 第2の基板
203 半導体チップ
204 第1のコロイド
205 第2のコロイド
201A 第1の表面
201B 第1の裏面
202A 第2の表面
202B 第2の裏面
202C 下面
202D 出光面
2011 配線パターン層
2012 配線パターン層
2021 第1の半田収容部
2022 第2の半田収容部
2024 電極
2026、2027 半田
Claims (20)
- 第1の基板と、第2の基板と、半導体チップとを含む半導体パッケージ構造であって、
前記第1の基板は、台座、第1の突出部および第2の突出部を含み、前記台座は、第1の表面、第1の側面及び第2の側面を含み、前記第1の突出部および前記第2の突出部は、前記第1の側面および前記第2の側面からそれぞれ延出しており、第1の接続面および第2の接続面をそれぞれ含み、前記第1の接続面および前記第2の接続面は、前記第1の側面および前記第2の側面にそれぞれ接続され、
前記第2の基板は、第2の表面を含み、前記第1の基板は、前記第2の表面の一部に配置され、
前記半導体チップは、前記台座の第1の表面に配置される、
半導体パッケージ構造。 - 前記第1の基板は、さらに配線パターン層を含み、前記配線パターン層は、前記台座の第1の表面、前記第1の側面及び前記第2の側面に配置され、前記半導体チップに電気的に接続される請求項1に記載の半導体パッケージ構造。
- 前記第1の基板は、さらに配線パターン層を含み、前記配線パターン層は、前記台座の第1の表面と、前記第1の突出部の前記第1の接続面と、前記第2の突出部の前記第2の接続面とに配置され、前記半導体チップに電気的に接続される請求項1に記載の半導体パッケージ構造。
- 前記第1の基板と前記第2の基板との間には、第1の切り欠けと第2の切り欠けが形成されており、前記第1の切り欠けは、前記第2の表面、前記第1の側面および前記第1の接続面の間に形成され、前記第2の切り欠けは、前記第2の表面、前記第2の側面および前記第2の接続面の間に形成される請求項1〜3のいずれか1項に記載の半導体パッケージ構造。
- 前記第2の基板は、さらに裏面と、別の配線パターン層とを含み、前記裏面は、前記第2の表面に電気的に接続され、前記別の配線パターン層は、前記裏面に配置される請求項1〜3のいずれか1項に記載の半導体パッケージ構造。
- 請求項1〜3のいずれか1項に記載の半導体パッケージ構造と回路基板を含む電子デバイスであって、
前記回路基板は、開口を含み、前記半導体パッケージ構造の前記第1の基板および前記第2の基板は、部分的に前記開口の中に位置し、前記半導体パッケージ構造は、前記回路基板に電気的に接続される、
電子デバイス。 - 前記回路基板は、第1の支持部および第2の支持部をさらに含み、前記第1の支持部と前記第2の支持部は、前記開口によって分離されており、前記第1の突出部および前記第2の突出部は、前記第1の支持部および前記第2の支持部にそれぞれ位置する請求項6に記載の電子デバイス。
- 前記半導体チップは、前記開口の中に位置する請求項6に記載の電子デバイス。
- 第1の基板と、第2の基板と、半導体チップとを含む半導体パッケージ構造であって、
前記第1の基板は、第1の表面および第1の裏面を含み、
前記第2の基板は、第2の表面、第2の裏面、下面および複数の第1の半田収容部を含み、前記複数の第1の半田収容部は、前記下面に配置され、前記第1の基板は、前記第2の表面に配置され、前記第1の基板と前記第2の基板は電気的に接続され、
前記半導体チップは、前記第1の表面に配置され、前記第1の基板に電気的に接続される、
半導体パッケージ構造。 - 前記複数の第1の半田収容部のそれぞれは溝を含み、前記第2の基板は複数の電極を含み、前記複数の電極はそれぞれ前記複数の第1の半田収容部の中に露出する請求項9に記載の半導体パッケージ構造。
- 前記複数の第1の半田収容部のそれぞれは、前記第2の表面及び前記第2の裏面を貫通する開口を含む請求項9に記載の半導体パッケージ構造。
- 前記複数の第1の半田収容部は、それぞれ前記下面の2つの側縁または2つの片隅に位置する請求項9〜11のいずれか1項に記載の半導体パッケージ構造。
- 前記第2の基板は、さらに第2の半田収容部を含み、前記第2の半田収容部は、前記下面に配置されて前記複数の第1の半田収容部の間に位置する請求項9〜11のいずれか1項に記載の半導体パッケージ構造。
- 第1のコロイドと第2のコロイドをさらに含み、前記第1のコロイドは前記半導体チップを覆い、前記第2のコロイドは前記第1のコロイドを取り囲み、前記第1のコロイドの出光面を露出させる請求項9〜11のいずれか1項に記載の半導体パッケージ構造。
- 前記第1の基板は、更に配線パターン層を含み、前記配線パターン層は、前記第1の表面に配置され、前記半導体チップに電気的に接続され、前記第2のコロイドにより囲まれる請求項14に記載の半導体パッケージ構造。
- 前記第1のコロイドはシリコーンであり、前記シリコーンは親水性シリカを含有する請求項14に記載の半導体パッケージ構造。
- 前記シリコーンは、フェニル基系のシリコーンであり、前記親水性シリカは、親水性ヒュームドシリカ(fumed silica)である請求項16に記載の半導体パッケージ構造。
- 前記シリコーンはさらに、シラノール基(silanol group)と水素結合を形成できる添加物を含有する請求項16に記載の半導体パッケージ構造。
- 前記添加物は、エポキシ基(epoxy)、メタクリルオキシ基(Methacryloxy)およびイソシアナト基(isocyanato)の少なくとも1つを含有する請求項18に記載の半導体パッケージ構造。
- 請求項9〜11のいずれか1項に記載の半導体パッケージ構造と回路基板を含む電子デバイスであって、
前記回路基板は、開口を含み、前記半導体パッケージ構造は、部分的に前記開口の中に位置し、前記半導体パッケージ構造は、前記回路基板に電気的に接続される、
電子デバイス。
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JP7490032B2 (ja) | 2022-04-24 | 2024-05-24 | 弘▲凱▼光▲電▼(江▲蘇▼)有限公司 | パッケージ構造及び表示装置 |
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EP3503226A2 (en) | 2019-06-26 |
KR20190023046A (ko) | 2019-03-07 |
EP3503226A3 (en) | 2019-09-18 |
EP3451395A2 (en) | 2019-03-06 |
US10559728B2 (en) | 2020-02-11 |
CN109427704A (zh) | 2019-03-05 |
US20190259924A1 (en) | 2019-08-22 |
TW201914058A (zh) | 2019-04-01 |
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TWI683454B (zh) | 2020-01-21 |
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