JP2018527754A5 - - Google Patents

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Publication number
JP2018527754A5
JP2018527754A5 JP2018513651A JP2018513651A JP2018527754A5 JP 2018527754 A5 JP2018527754 A5 JP 2018527754A5 JP 2018513651 A JP2018513651 A JP 2018513651A JP 2018513651 A JP2018513651 A JP 2018513651A JP 2018527754 A5 JP2018527754 A5 JP 2018527754A5
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JP
Japan
Prior art keywords
dielectric layer
conductive pads
cavities
conductors
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2018513651A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018527754A (ja
JP6549790B2 (ja
Filing date
Publication date
Priority claimed from US14/859,323 external-priority patent/US10074625B2/en
Application filed filed Critical
Publication of JP2018527754A publication Critical patent/JP2018527754A/ja
Publication of JP2018527754A5 publication Critical patent/JP2018527754A5/ja
Application granted granted Critical
Publication of JP6549790B2 publication Critical patent/JP6549790B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2018513651A 2015-09-20 2016-09-20 キャビティ構造を使用するウェハレベルパッケージ（ｗｌｐ）ボール支持体 Expired - Fee Related JP6549790B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/859,323 US10074625B2 (en) 2015-09-20 2015-09-20 Wafer level package (WLP) ball support using cavity structure
US14/859,323 2015-09-20
PCT/US2016/052631 WO2017049324A1 (en) 2015-09-20 2016-09-20 Wafer level package (wlp) ball support using cavity structure

Publications (3)

Publication Number Publication Date
JP2018527754A JP2018527754A (ja) 2018-09-20
JP2018527754A5 true JP2018527754A5 (https=) 2018-11-29
JP6549790B2 JP6549790B2 (ja) 2019-07-24

Family

ID=57018210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018513651A Expired - Fee Related JP6549790B2 (ja) 2015-09-20 2016-09-20 キャビティ構造を使用するウェハレベルパッケージ（ｗｌｐ）ボール支持体

Country Status (8)

Country Link
US (1) US10074625B2 (https=)
EP (1) EP3350831A1 (https=)
JP (1) JP6549790B2 (https=)
KR (1) KR102006115B1 (https=)
CN (1) CN108028243B (https=)
BR (1) BR112018005532B1 (https=)
CA (1) CA2995621A1 (https=)
WO (1) WO2017049324A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240057513A (ko) 2022-10-24 2024-05-03 삼성전자주식회사 반도체 패키지

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* Cited by examiner, † Cited by third party
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JP3070514B2 (ja) * 1997-04-28 2000-07-31 日本電気株式会社 突起電極を有する半導体装置、半導体装置の実装方法およびその実装構造
GB2389460A (en) 1998-12-22 2003-12-10 Nec Corp Mounting semiconductor packages on substrates
JP3019851B1 (ja) * 1998-12-22 2000-03-13 日本電気株式会社 半導体装置実装構造
JP3446825B2 (ja) * 1999-04-06 2003-09-16 沖電気工業株式会社 半導体装置およびその製造方法
JP2002050716A (ja) * 2000-08-02 2002-02-15 Dainippon Printing Co Ltd 半導体装置及びその作製方法
JP3842548B2 (ja) * 2000-12-12 2006-11-08 富士通株式会社 半導体装置の製造方法及び半導体装置
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
JP2003198068A (ja) 2001-12-27 2003-07-11 Nec Corp プリント基板、半導体装置、およびプリント基板と部品との電気的接続構造
US6854633B1 (en) * 2002-02-05 2005-02-15 Micron Technology, Inc. System with polymer masking flux for fabricating external contacts on semiconductor components
JP2004103928A (ja) * 2002-09-11 2004-04-02 Fujitsu Ltd 基板及びハンダボールの形成方法及びその実装構造
US7043830B2 (en) 2003-02-20 2006-05-16 Micron Technology, Inc. Method of forming conductive bumps
US8193092B2 (en) * 2007-07-31 2012-06-05 Micron Technology, Inc. Semiconductor devices including a through-substrate conductive member with an exposed end and methods of manufacturing such semiconductor devices
WO2009104506A1 (ja) * 2008-02-19 2009-08-27 日本電気株式会社 プリント配線板、電子装置及びその製造方法
JP2012221998A (ja) * 2011-04-04 2012-11-12 Toshiba Corp 半導体装置ならびにその製造方法
JP5682496B2 (ja) * 2011-07-28 2015-03-11 富士通セミコンダクター株式会社 半導体装置、マルチチップ半導体装置、デバイス、及び半導体装置の製造方法
KR101840447B1 (ko) * 2011-08-09 2018-03-20 에스케이하이닉스 주식회사 반도체 패키지 및 이를 갖는 적층 반도체 패키지
JP2013074054A (ja) * 2011-09-27 2013-04-22 Renesas Electronics Corp 電子装置、配線基板、及び、電子装置の製造方法
JP2013080805A (ja) * 2011-10-03 2013-05-02 Sumitomo Bakelite Co Ltd 補強部材の製造方法
US9129973B2 (en) * 2011-12-07 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit probing structures and methods for probing the same
EP2605273A3 (en) * 2011-12-16 2017-08-09 Imec Method for forming isolation trenches in micro-bump interconnect structures and devices obtained thereof
US8963336B2 (en) * 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
US8963335B2 (en) 2012-09-13 2015-02-24 Invensas Corporation Tunable composite interposer
US9343419B2 (en) * 2012-12-14 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
EP2747132B1 (en) * 2012-12-18 2018-11-21 IMEC vzw A method for transferring a graphene sheet to metal contact bumps of a substrate for use in semiconductor device package
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US9484318B2 (en) * 2014-02-17 2016-11-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US20150237732A1 (en) 2014-02-18 2015-08-20 Qualcomm Incorporated Low-profile package with passive device

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