CN104752372B - 模封组件及模封材料 - Google Patents

模封组件及模封材料 Download PDF

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Publication number
CN104752372B
CN104752372B CN201410552591.3A CN201410552591A CN104752372B CN 104752372 B CN104752372 B CN 104752372B CN 201410552591 A CN201410552591 A CN 201410552591A CN 104752372 B CN104752372 B CN 104752372B
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molding
semiconductor element
warpage
substrate
molding material
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CN104752372A (zh
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林育民
詹朝杰
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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Abstract

本发明公开一种模封组件及模封材料，该模封组件包括基板及堆叠于其上的第一模封件和第二模封件，该第一或第二模封件分别具有半导体元件、位于半导体元件周围的翘曲抑制结构、包覆半导体元件及翘曲抑制结构的模封材料、及位于半导体元件、模封材料和翘曲抑制结构上的保护层。一种模封材料，包括本体及设于本体内的翘曲抑制结构，翘曲抑制结构包含位于本体内边缘的环状部、位于该环状部内侧的格栅以及连接该环状部与该格栅的连接部。因此，本发明可避免模封组件于制作过程中产生翘曲。

Description

模封组件及模封材料
技术领域
本发明涉及一种模封组件及模封材料，尤其是涉及一种可抵抗翘曲的模封材料及模封组件。
背景技术
在电子封装领域中，有些应用架构是必须在芯片对晶片组装(CoW assembly)之后，进行模封作业(molding process)以及晶片薄化作业(wafer thinning)。
影响电子产品良率的因素包括芯片高度均匀性、芯片分布均匀性、模封材料与芯片的硬度、刚性、热膨胀系数、玻璃转化温度等性质、晶片的翘曲量、翘曲均匀性等性质。
目前发现，在经过模封作业后，整体模封件会出现严重的翘曲现象，导致要进行后续研磨作业时，研磨机台无法有效吸真空。再者，即使研磨机台可以吸真空，却发现研磨完成后晶片的边缘外露于模封材料外，因此，薄化过程中轻微的翘曲或芯片的分布仍会影响整体的薄化均匀度。另外，翘曲也有可能导致后续可靠度的问题产生。
因此，防止晶片的翘曲是业界极待解决的课题。
发明内容
本发明的目的在于提供一种模封组件及模封材料，可避免模封组件于制作过程中产生翘曲。
为达上述目的，本发明的模封组件包含：基板，具有相对的第一表面及第二表面；第一模封件，位于该基板的该第一表面上，该第一模封件包含：第一导电元件，位于该基板的该第一表面上；第一半导体元件，通过该第一导电元件而与该基板电连接；第一翘曲抑制结构，位于该第一半导体元件的周围；第一模封材料，位于该基板的第一表面上，用于包覆该第一半导体元件、该第一导电元件及第一翘曲抑制结构；以及第一保护层，位于该第一半导体元件、该第一模封材料及该第一翘曲抑制结构上；以及第二模封件，位于该第一模封件上，包含：第二导电元件，位于该第一半导体元件上；第二半导体元件，通过该第二导电元件而与该第一半导体元件电连接；第二翘曲抑制结构，位于该第二半导体元件的周围；第二模封材料，位于该第一模封件的该第一保护层上，用于包覆该第二半导体元件、该第二导电元件及该第二翘曲抑制结构；以及第二保护层，位于该第二半导体元件、该第二模封材料及该第二翘曲抑制结构上。
本发明的模封组件还包含第三模封件位于该第二模封件上，包含：第三导电元件，位于该第二半导体元件上；第三半导体元件，通过该第三导电元件而与该第二半导体元件电连接；第三翘曲抑制结构，位于该第三半导体元件的周围；以及第三模封材料，位于该第二模封件的该第二保护层上，用于包覆该第三半导体元件、该第三导电元件及该第三翘曲抑制结构。该第三模封件还包括第三保护层，位于该第三半导体元件、该第三模封材料及该第三翘曲抑制结构上。
本发明的模封组件还包含第四导电元件位于该基板的该第二表面，其中该基板、该第一半导体元件和该第二半导体元件分别具有多个贯穿电极。
本发明还提供一种模封材料，包括：本体；以及翘曲抑制结构，包含：位于该本体内的边缘的环状部、位于该环状部的内侧的格栅以及连接该环状部与该格栅的连接部，该翘曲抑制结构用于防止该模封材料于模封程序时的翘曲。
上述的模封材料包含平行堆叠的第一材料层及第二材料层，该第一材料层中的粒子尺寸小于该第二材料层的粒子尺寸。上述翘曲抑制结构的材料硬度大于硅。
相较于先前技术，本发明的模封材料中设计有翘曲抑制结构，于制作模封组件而于模封程序中防止翘曲的产生，并有益于后续的薄化作业。
附图说明
图1为本发明的模封件的第一实施例的俯视示意图；
图2A至图2D为本发明的模封件的第一实施例的制法示意图；
图3为本发明的模封件的第二实施例的俯视示意图；
图4A至图4D为本发明的模封件的第二实施例的制法示意图；
图5A为本发明的模封件的第三实施例的俯视示意图；
图5B为本发明的模封材料的剖视示意图；
图5C为本发明的模封件的第三实施例的剖视示意图；
图6为本发明的模封件的第四实施例的剖视示意图；以及
图7A至图7E为本发明的模封组件的制作流程示意图，其中，图7D’为图7D的进一步实施例，图7E’为图7E的进一步实施例。
符号说明
1基板 11第一表面
12第二表面 13、31、631、731贯穿电极
2导电元件 3半导体元件
4模封材料 41第二材料层
42第一材料层 5翘曲抑制结构
51第一环状部 52第二环状部
53连接部 54格栅
6第一模封件 62第一导电元件
63第一半导体元件 64第一模封材料
65第一翘曲抑制结构
66第一保护层 7第二模封件
72第二导电元件 73第二半导体元件
74第二模封材料 75第二翘曲抑制结构
76第二保护层 8第四导电元件
9第三模封件 92第三导电元件
93第三半导体元件 94第三模封材料
95第三翘曲抑制结构
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，熟悉此项技术的人士可由本文所揭示的内容轻易地了解本发明的其他优点及功效。
需知，本说明书所附的附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“第一或第二”及“上”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
参阅图1配合图2A至图2D，其中，图1绘示本发明的模封件的第一实施例的俯视示意图，图2A至图2D绘示本发明的模封件的第一实施例的制作流程示意图。在本实施例中，模封件主要包括基板1、半导体元件3、模封材料4及翘曲抑制结构5。
基板1具有第一表面11，基板1的外型为圆形或矩形。半导体元件3，例如芯片，或者为MEMS(Micro Electro Mechanical System)元件，通过导电元件2设置于基板1的第一表面11上，半导体元件3与基板1之间填充有底部填充胶(underfill)(未标号)。模封材料4形成于基板1的第一表面11上以包覆半导体元件3。
翘曲抑制结构5位于模封材料4内的边缘，且大致呈环状。翘曲抑制结构5由较硅或较模封材料4为硬的材料组成，例如玻璃纤维、碳纤维或添加有大量硅填充物的材料等等。翘曲抑制结构5的外型为圆形或矩形。
接着，以图2A至图2D说明图1的第一实施例的模封件的制法。如图2A所示，将半导体元件3设置于基板1的第一表面11上，其中，半导体元件3通过导电元件2与基板1电连接，且半导体元件3和基板1之间填充有底部填充胶(未标号)，而半导体元件3具有贯穿电极(Through-Silicon Via；TSV)31。需说明的是，此图仅示意而非限制半导体元件3的数量。如图2B所示，提供一内置有翘曲抑制结构5的模封材料4，而翘曲抑制结构5位于模封材料4内的边缘且大致呈环状。如图2C所示，将内置有翘曲抑制结构5的模封材料4压合于基板1上以包覆半导体元件3，则翘曲抑制结构5位于半导体元件3的周围。如图2D所示，最后研磨模封材料4以使贯穿电极31外露。
由此，在本实施例中，本发明的模封件由于在模封材料4内置有翘曲抑制结构5，故可避免模封件的翘曲。
参阅图3配合图4A至图4D，其中，图3绘示本发明的模封件的第二实施例的俯视示意图，图4A至图4D绘示本发明的模封件的第二实施例的制作流程示意图。
本实施例与第一实施例的差异在于，翘曲抑制结构5具有位于模封材料4的边缘的第一环状部51、位于模封材料4的中央的第二环状部52以及连接第一环状部51与第二环状部52的连接部53。如图3所示，模封件包括但不限于多个半导体元件3，翘曲抑制结构5的第二环状部52位于模封材料4的中央以围绕于位于中央的半导体元件3，而其第一环状部51位于模封材料4的边缘以围绕全部的半导体元件3，且第一环状部51和第二环状部52又以连接部53相互连接，使得模封材料4于其中央及边缘都有支撑，故可避免模封件的翘曲。此外，同样地，翘曲抑制结构5可由较硅或较模封材料4为硬的材料组成，例如玻璃纤维、碳纤维或添加有大量硅填充物材料等等。
图4A至图4D所示的制法基本上与图2A至图2D相似，其差异仅在于翘曲抑制结构的样貌，故在此不予以赘述。
参阅图5A、图5B及图5C，其中，图5A绘示本发明的模封件的第三实施例的俯视示意图，图5B绘示本发明的模封材料的剖视示意图，图5C绘示本发明的模封件的第三实施例的剖视示意图。
本实施例与第一实施例的差异在于，如图5A和图5B所示，翘曲抑制结构5包含位于模封材料4的边缘的第一环状部51、位于第一环状部51的内侧的格栅54以及连接第一环状部51与格栅54的连接部53，而半导体元件3的数量为多个且呈阵列排列，格栅54围绕所述半导体元件3且介于所述半导体元件3之间。由此，在本实施例中，每一半导体元件3的周围及全部半导体元件3的外围都环绕有翘曲抑制结构，故可避免模封件的翘曲。
图6绘示本发明的模封件的第四实施例的剖视示意图。在本实施例中，模封件主要包括基板1、半导体元件3、模封材料4及翘曲抑制结构5。
基板1具有第一表面11，基板1的外型为圆形或矩形。导电元件2设置于基板1的第一表面11上。半导体元件3，例如芯片，或者为MEMS(Micro Electro Mechanical System)元件，通过导电元件2设置于基板1的第一表面11之上。
模封材料4形成于基板1的第一表面11上并包覆半导体元件3，模封材料4包含平行堆叠的第二材料层41及第一材料层42，且第一材料层42填充于半导体元件3与基板1之间以包覆导电元件2，如图6所示，翘曲抑制结构5位于模封材料4的第二材料层41与第一材料层42内。第二材料层41与第一材料层42的材料为相同或相异，在材料相异时，第二材料层41中的粒子尺寸大于第一材料层42中的粒子尺寸，且第一材料层42可由与基板1性质相似的材料组成。在材料相同时，可分次或同时形成，分次形成，例如，先于半导体元件3与基板1之间填充第一材料层42以包覆导电元件2，再以利用第二材料层41组成的模封材料4包覆半导体元件3；同时形成例如，直接以第二材料层41组成的模封材料4压合于基板1上以包覆半导体元件3和导电元件2。
翘曲抑制结构5位于模封材料4内的边缘，且大致呈环状。翘曲抑制结构5由较硅或较模封材料4为硬的材料组成，例如玻璃纤维、碳纤维或添加有大量硅填充物材料等等，翘曲抑制结构5的外型为圆形或矩形。另外，在本实施例中，翘曲抑制结构5可为如图1所示呈环状，或如图3所示包含位于模封材料4的边缘的第一环状部51、位于模封材料4的中央的第二环状部52以及连接第一环状部51与第二环状部52的连接部53，或如图5所示包含位于模封材料4的边缘的第一环状部51、位于第一环状部51的内侧的格栅54以及连接第一环状部51与格栅54的连接部53。
由此，模封材料4的第一材料层42可替代底部填充胶，直接将包含第二材料层41和第一材料层42的模封材料4压合于基板1上，使第二材料层41包覆半导体元件3而使第一材料层42填充于半导体元件3与基板1之间以包覆导电元件2。因此，本实施例可于制作工艺时免去点胶的步骤。
另外，图7A至图7E说明本发明的模封组件的制作流程示意图。
如图7A所示，基板1的第一表面11上设置有多个具有贯穿电极631的第一半导体元件63，第一半导体元件63与基板1之间以第一导电元件62相互电连接，第一模封材料64形成于基板1的第一表面11上以包覆第一半导体元件63与第一导电元件62，第一翘曲抑制结构65设置于第一模封材料64中，且多个第一半导体元件63的周围都有第一翘曲抑制结构65。例如，基板1可为硅基板、有机基板或中介板。又，第一模封材料64及其中的第一翘曲抑制结构65基本上与图5A和图5B所示的模封材料4及其中的翘曲抑制结构5相同。基板1的外型为圆形或矩形，第一半导体元件63可为MEMS元件，第一翘曲抑制结构65的外型为圆形或矩形。
如图7B所示，在第一半导体元件63、第一模封材料64及第一翘曲抑制结构65上形成第一保护层66，此时，第一半导体元件63、第一模封材料64、第一翘曲抑制结构65和第一保护层66形成第一模封件6。接着，在第一保护层66对应第一半导体元件63的贯穿电极631之处形成开口(未标号)，再于该开口中形成连接贯穿电极631的第二导电元件72。此外，因应第一导电元件62位置分布不同的需求，贯穿电极631上可经过线路重布(RDL)而更改其开口以及第一导电元件62位置。
接着，如图7C和图7D所示，在第一模封件6上形成第二模封件7。
如图7C所示，在第一模封件6上设置多个具有贯穿电极731的第二半导体元件73以利用第二导电元件72与第一模封件6电连接。接着，将其中设置有第二翘曲抑制结构75的第二模封材料74压合于第一保护层66上，以包覆第二半导体元件73及第二导电元件72，又，第二模封材料74及其中的第二翘曲抑制结构75基本上与图5A和图5B所示的模封材料4及其中的翘曲抑制结构5相同，使得当第二模封材料74压合于第一模封件6上时，各个第二半导体元件73的周围都有第二翘曲抑制结构75。第二翘曲抑制结构75的外型为圆形或矩形，第二半导体元件73可为MEMS元件。
接着，如图7D所示，再于第二半导体元件73、第二模封材料74和第二翘曲抑制结构75形成第二保护层76。此外，因应第二导电元件72位置分布不同的需求，贯穿电极731上可经过线路重布(RDL)而更改其开口以及第二导电元件72位置。
最后，对图7D所示的结构执行切割，以完成图7E所示的模封组件，由此，完成本发明的包括基板1、第一模封件6和第二模封件7的模封组件。另外，在基板1中形成贯穿电极13以及于基板1的第二表面12形成电连接贯穿电极13的第四导电元件8。
另外，如图7D’所示，在第二保护层76上再形成以第三导电元件92与第二模封件7电连接的第三模封件9，最后，对图7D’所示的结构执行切割，以完成图7E’所示的模封组件，由此，完成本发明的包括基板1、第一模封件6、第二模封件7和第三模封件9的模封组件。
由图7A至图7E和图7D’和图7E’可知，本发明可于第二模封件7上垂直堆叠多个模封件。需说明的是，图7D’仅为示意，若本发明的模封组件仅包括基板1、第一模封件6、第二模封件7和第三模封件9，则位于最外层的第三半导体元件93并不需具有贯穿电极，且其中设置有第三翘曲抑制结构95的第三模封材料94上也不需再形成第三保护层。另一方面，于第二模封件7上堆叠有多层彼此电连接的模封件时，这些模封件的结构与第一模封件6和第二模封件7相同，仅最外层的模封件无具有保护层及模封件中的半导体元件无具有贯穿电极。
此外，图7A至图7E和图7D’和图7E’中的第一模封材料64、第二模封材料74或第三模封材料94都可同图6所示的模封材料4般包含平行堆叠的二材料层，例如，第一模封材料64包含第一材料层42填充于第一半导体元件63与基板1之间，以及第二材料41层覆盖第一半导体元件63与第一材料层42；第二模封材料74包含第三材料层(未绘示)填充于第二半导体元件73与第一模封件6之间，以及第四材料层覆盖第二半导体元件73与该第三材料层。
综上所述，本发明的模封组件包含基板及堆叠于其上的至少一模封件，各模封件具有半导体元件、位于半导体元件周围的翘曲抑制结构、包覆半导体元件及翘曲抑制结构的模封材料、及位于半导体元件、模封材料和翘曲抑制结构上的保护层。此外，本发明主要在压合于基板上的模封材料中设计一翘曲抑制结构，其含有位于模封材料内的边缘的第一环状部、位于第一环状部内侧的格栅及连接第一环状部与格栅的连接部，由此，翘曲抑制结构可提供模封材料支撑力，可于模封程序时抑制基板(晶片)的翘曲，更有益于后续的薄化作业。另外，本发明的模封材料可包含平行堆叠的二材料层，其中一材料层可代替底部填充胶而充填于半导体元件(芯片)与基板(晶片)之间，故可免于点胶的步骤而达到制作工艺加速的功效。
上述实施例仅例示性说明本发明的功效，而非用于限制本发明，任何熟悉此项技术的人士均可在不违背本发明的精神及范畴下，对上述实施例进行修饰与改变。此外，在上述实施例中的结构的数量仅为例示性说明，也非用于限制本发明。因此本发明的权利保护范围，应如权利要求书所列。

Claims (15)

1.一种模封组件，包含：
基板，具有相对的第一表面及第二表面；
第一模封件，位于该基板的该第一表面上，该第一模封件包含：
第一导电元件，位于该基板的该第一表面上；
第一半导体元件，通过该第一导电元件与该基板电连接；
第一模封材料，包含：第一本体，位于该基板的该第一表面上，用于包覆该第一半导体元件、该第一导电元件；以及第一翘曲抑制结构，嵌埋于该第一本体中，并且该第一翘曲抑制结构具有环状部，位于该第一本体内的边缘，且位于该第一半导体元件的周围，用于防止该第一模封件的翘曲；以及
第一保护层，位于该第一半导体元件、该第一模封材料及该第一翘曲抑制结构上；以及
第二模封件，位于该第一模封件上，包括：
第二导电元件，位于该第一半导体元件上；
第二半导体元件，通过该第二导电元件与该第一半导体元件电连接；
第二模封材料，包括：第二本体，位于该第一模封件的该第一保护层上，用于包覆该第二半导体元件、该第二导电元件；以及第二翘曲抑制结构，嵌埋于该第二本体中，并且该第二翘曲抑制结构具有环状部，位于该第二本体内的边缘，且位于该第二半导体元件的周围，用于防止该第二模封件的翘曲；以及
第二保护层，位于该第二半导体元件、该第二模封材料及该第二翘曲抑制结构上。
2.如权利要求1所述的模封组件，其特征为，该模封组件还包含位于该第二模封件上的第三模封件，包含：
第三导电元件，位于该第二半导体元件上；
第三半导体元件，通过该第三导电元件与该第二半导体元件电连接；
第三翘曲抑制结构，位于该第三半导体元件的周围；以及
第三模封材料，位于该第二模封件的该第二保护层上，用于包覆该第三半导体元件、该第三导电元件、以及该第三翘曲抑制结构。
3.如权利要求2所述的模封组件，其特征为，该模封组件还包含位于该基板的该第二表面的第四导电元件，其中该基板、该第一半导体元件和该第二半导体元件分别包含多个贯穿电极，该基板、该第一半导体元件和该第二半导体元件通过所述贯穿电极与该第四导电元件电连接。
4.如权利要求2所述的模封组件，其特征为，该第三模封件还包括第三保护层，其位于该第三半导体元件、该第三模封材料及该第三翘曲抑制结构上。
5.如权利要求1所述的模封组件，其特征为，该第一翘曲抑制结构与该第二翘曲抑制结构的材料硬度大于硅。
6.如权利要求1所述的模封组件，其特征为，该第一翘曲抑制结构及该第二翘曲抑制结构的材料为玻璃纤维或添加有硅填充物的材料。
7.如权利要求1所述的模封组件，其特征为，该基板为硅基板、有机基板、中介板、或有贯穿电极的基板。
8.如权利要求1所述的模封组件，其特征为，该第一模封材料包含第一材料层填充于该第一半导体元件与该基板之间，以及第二材料层覆盖该第一半导体元件与该第一材料层；其中该第二模封材料包含第三材料层填充于该第二半导体元件与该第一模封件之间，以及第四材料层覆盖该第二半导体元件与该第三材料层。
9.如权利要求1所述的模封组件，其特征为，该基板的外型为圆形或矩形，该第一翘曲抑制结构的外型为圆形或矩形，该第二翘曲抑制结构的外型为圆形或矩形。
10.如权利要求1所述的模封组件，其特征为，该第一半导体元件为微机电元件，该第二半导体元件为微机电元件。
11.一种模封材料，包含：
本体；以及
翘曲抑制结构，嵌埋于该本体中，该翘曲抑制结构包含：
环状部，位于该本体内的边缘；
格栅，位于该环状部的内侧；以及
连接部，连接该环状部与该格栅；
其中该翘曲抑制结构用于防止该模封材料于模封程序时的翘曲。
12.如权利要求11所述的模封材料，其特征为，该模封材料包含第一材料层与第二材料层。
13.如权利要求12所述的模封材料，其特征为，该第一材料层中的粒子尺寸小于该第二材料层的粒子尺寸。
14.如权利要求11所述的模封材料，其特征为，该翘曲抑制结构的材料硬度大于硅。
15.如权利要求11所述的模封材料，其特征为，该本体的外型为圆形或矩形，该翘曲抑制结构的外型为圆形或矩形。
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